Semiconductor device including bit line formed using damascene technique and method of fabricating the same

Abstract

A semiconductor device includes an insulating layer having a T-shaped groove formed by a wide opening overlapping a narrow opening, a bit line conductive layer that at least partially fills the narrow opening, and a bit line capping layer that fills the groove so that its top surface is as high as that of the insulating layer. Spacers are formed on the inner walls of the wide opening.

Description

CROSS REFERENCES TO RELATED APPLICATIONS [0001] This is a divisional application of U.S. application Ser. No. 10 / 703,328 filed on Nov. 7, 2003, the disclosure of which is herein incorporated by reference in its entirety.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to a semiconductor device having conductive layers, such as bit lines, which are closely formed to be parallel, and a method of fabricating the same. [0004] 2. Description of the Related Art [0005] As the integration density of semiconductor memory devices, such as DRAMs, increases, more attention is being paid to methods of minimizing chip size. In recent years, DRAM cells having a design rule of 0.11 μm or less have been developed. However, as the design rule and chip size of DRAMs decrease, overcoming restrictions of photolithographic processes used to form...

AI Technical Summary

Benefits of technology

The present invention provides a method and structure for fabricating a semiconductor device with bit lines that can be easily formed and have a sufficient margin of process margin. The method includes forming an insulating layer on a substrate, etching the insulating layer to a partial depth, and forming spacers on the inner walls of the etched insulating layer. A conductive layer is then formed to fill the opening, followed by a capping layer to fill the groove. The invention also provides a semiconductor device with a bit line structure that includes a T-shaped groove, a bit line conductive layer that fills the narrow opening, and a bit line capping layer that fills the groove. The bit line conductive layer includes a stack of layers, and the interface between the spacer and insulating layer is flat. The invention also allows for the formation of a bit line with a reduced design rule and minimizes misalignment between the bit line and other conductive elements. The invention can be applied to various conductive layers, such as interconnections or gate lines.

Problems solved by technology

However, as the design rule and chip size of DRAMs decrease, overcoming restrictions of photolithographic processes used to form the DRAMs and securing a sufficient process margin become more complicated.

However, the foregoing conventional method using photolithographic exposure equipment cannot obtain finer bit line patterns.

Thus, sufficiently reducing the cell size becomes difficult.

Also, the misalignment margin between a bit line and a bit line contact plug may be reduced, thus causing problems such as leakage.

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