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TSV Formation Method

A technology of through-silicon vias and morphology, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of easy leakage, poor interconnection structure quality of through-silicon vias, etc., and achieve the effect of slowing down the offset phenomenon

Active Publication Date: 2016-04-13
ADVANCED MICRO FAB EQUIP INC CHINA
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Problems solved by technology

[0004] However, the main technical difficulty faced by the through-silicon via interconnection structure lies in the need to etch via holes with a relatively high aspect ratio (AspectRatio) and control the profile of via holes with a high aspect ratio. TSV interconnect structure is of poor quality and prone to leakage

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Embodiment Construction

[0022] Research has been carried out on TSV products with serious leakage phenomena. After analyzing the cross-section of the TSV formed by the prior art with a scanning electron microscope, it is found that the morphology of the TSV formed by the existing process is as follows: figure 1 Shown is scalloped, serrated or corrugated to a greater degree, with higher roughness. Form an insulating layer on the surface of a shell-shaped, jagged or corrugated through-hole with high roughness, and then fill it with a conductive substance. The uniformity of the insulating layer is difficult to control, so that the conductive substance along the thinner position of the insulating layer Diffusion into the wafer, resulting in serious leakage of TSV products.

[0023] After further research on the process of forming the through-silicon vias, it was found that the reason for the formation of the surface of the above-mentioned corrugated through-holes is that in the formation process of the t...

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Abstract

Provided is a method for forming a through silicon via. The method comprises: obtaining a first etching stage and a second etching stage according to a through silicon via to be formed; etching a silicon substrate with a first Bosch process in the first etching stage at a first etching temperature in order to form a first via; and etching the silicon substrate with a second Bosch process along the first via in the second etching stage at a second etching temperature until a through silicon via is formed, wherein the second Bosch process comprises: etching the silicon substrate with the first etching in order to form an opening; forming a protection layer on the sidewall and the bottom of the opening with passivation deposition; and successively and circularly using the first etching and the passivation deposition until the through silicon via is formed, wherein the second etching temperature is below the first etching temperature or over the first etching temperature. The through silicon via formed by using the method for forming a through silicon via has high quality.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming through-silicon holes. Background technique [0002] Through-Silicon Via (TSV, Through-Silicon-Via) interconnection structure is the latest technology to realize the interconnection between chips by making vertical conduction between chips and between wafers. Unlike previous IC package bonding and overlay technologies using bumps, the through-silicon via interconnect structure can maximize the density of chips stacked in three dimensions, minimize the size of the chip, and greatly improve the performance of chip speed and low power consumption. [0003] The method for forming the existing TSV interconnection structure can refer to the Chinese patent with the publication number CN101483150A, which includes the following steps: step S11, etching the through hole on the surface of the wafer; step S12, forming an insulating layer on the surface and bott...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
CPCH01L21/30655H01L21/76898
Inventor 严利均倪图强
Owner ADVANCED MICRO FAB EQUIP INC CHINA
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