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Self-alignment duplex patterning method

A double patterning and self-alignment technology, which is applied in the fields of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of complex process, poor shape of etched pattern sidewall, etc., and achieve the effect of reducing process steps

Active Publication Date: 2014-03-26
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0011] However, the inventors have found that the sidewall morphology of the etched pattern formed by etching the material layer to be etched using the above method is relatively poor, and the process is complicated.

Method used

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Embodiment Construction

[0035] Due to the poor morphology of the sidewall of the etched pattern formed by etching the material layer to be etched using the above-mentioned technology, and the complicated process, the inventors have found through research that when a hard surface is formed on the surface of the sacrificial material layer and the sacrificial photoresist layer When the hard mask layer is used, the hard mask layer will stress the sacrificial photoresist layer. Since the hardness of the photoresist layer is not high, the sacrificial photoresist layer is relatively soft even after exposure and baking, and the stress generated by the hard mask layer will deform the sacrificial photoresist layer, forming a trapezoidal cross section. Sacrifice the photoresist layer, so that the sidewall of the sacrificial photoresist layer is not perpendicular to the surface of the material layer to be etched, so that the sidewall subsequently formed on the sidewall surface of the sacrificial photoresist layer...

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Abstract

The invention provides a self-alignment duplex patterning method. The method comprises the following steps: providing a material layer to be etched, forming a sacrificial photoresist layer on the material layer to be etched, curing photoresist at the top and side wall of the sacrificial photoresist layer to form a cured photoresist casing, performing back-etching on the cured photoresist casing at the top of the sacrificial photoresist layer until an uncured inner sacrificial photoresist layer is exposed, forming a first mask pattern on the cured photoresist casing on the side wall of the inner sacrificial photoresist layer, and removing the uncured inner sacrificial photoresist layer. As a hard mask layer is not required to form, the process procedures are reduced, and the impact of the stress generated by the hard mask layer on the profile of the sacrificial photoresist layer is eliminated. Besides, the first mask pattern is formed by removing the top of the cured photoresist casing, the side wall of the sacrificial photoresist layer formed by the photolithographic process is smooth and perpendicular to the surface of the material layer to be etched, and the side wall of the finally-formed etched pattern has a better profile.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a self-alignment double patterning method. Background technique [0002] In the field of semiconductor manufacturing, photoresist materials are used to transfer mask images to one or more material layers, for example, transfer mask images to metal layers, dielectric layers or semiconductor substrates. However, as the feature size of the semiconductor process continues to shrink, it becomes more and more difficult to form a mask pattern with a small feature size in the material layer by using a photolithography process. [0003] In order to improve the integration level of semiconductor devices, various double patterning processes have been proposed in the industry, among which the self-aligned double patterning (Self-Aligned Double Patterning, SADP) process is one of them. Figure 1 to Figure 6 A method for etching a semiconductor structure using a self-aligned double pattern as a mask...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/302H01L21/265
CPCH01L21/0337H01L21/0338H01L21/32139
Inventor 胡华勇
Owner SEMICON MFG INT (SHANGHAI) CORP
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