A kind of manufacturing method of split gate mosfet

Abstract

The invention discloses a method for fabricating a split gate MOSFET, comprising: step 1, forming an epitaxial layer on a substrate; step 2, depositing a first oxide layer on a first main surface; step 3, forming a trench; Fourth, remove the first oxide layer; step five, form a second oxide layer in the trench; step six, form a separation gate polysilicon in the trench; step seven, form an isolation oxide layer between polysilicon; step eight, in the trench forming a nitride layer; step 9, forming sacrificial polysilicon in the trench; step 10, removing the nitride layer above the sacrificial polysilicon to form a mask structure; step 11, using the mask structure as an etching mask to remove the inter-polysilicon isolating the second oxide layer above the oxide layer; step 12, removing the nitride layer to lift off the sacrificial polysilicon. In the present invention, the isolation oxide layer between polysilicons that meets the technological requirements can be formed at one time through the high-density plasma chemical vapor deposition method or the low-temperature wet oxidation method.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a split gate MOSFET. Background technique [0002] Trench power MOSFET is a new high-efficiency switching device developed after planar VDMOS. It is widely used in the field of power electronics due to its advantages of high input impedance, small driving current, fast switching speed, and good high temperature characteristics. High breakdown voltage, high current, and low on-resistance are the most critical indicators of power MOSFETs. The breakdown voltage is related to the on-resistance value. In the MOSFET design process, high breakdown voltage and low on-resistance cannot be obtained at the same time. balance between the two. [0003] In order to obtain a higher breakdown voltage and lower on-resistance as much as possible, a new type of MOSFET device with split gate structure has emerged. Compared with the common trench MOSFET structure, it...

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Problems solved by technology

[0005] 1. Poor insulation of the polysilicon isolation oxide layer (IPO, inter-poly oxide) between the source and the gate leads to an increase in gate-source leakage current Igss;

[0006] 2. The overlapping area between the source and the gate is too large, and the thickness of the isolation oxide layer between polysilicon is insufficient, resulting in a substantial increase in the capacitance Cgs between the source and the gate

[0007] The main reason that causes the above-mentioned shortcoming is, in the production technology of prior art, as Figure 2A to Figure 2D As shown, after wet etching removes the separation gate oxide layer on the side wall of the trench, the surface of the separation gate polysilicon will be higher than the separation gate oxide layer, and a recessed structure will be formed on both sides of the separation gate polysilicon, resulting in the subsequent formation of the gate oxide layer. When the isolation oxide layer between polysilicon and polysilicon is formed, because the thickness of the isolation oxide layer between polysilicon is very thin, it will form a "ㄇ" shape, which makes the insulation between the source and the gate poor and the overlapping area is too large, resulting in the above disadvantages

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