Semiconductor etching device and etching method for semiconductor structure

Abstract

Disclosed are a semiconductor etching device and an etching method of a semiconductor structure. The etching method includes: a etching process with a first bias power source is utilized to etch a to-be-etched material layer, and the first bias power source generates continuous bias power to form a first opening which does not expose a etching blocking layer; and then a etching process with a second bias power source is utilized to etch the first opening, and the second bias power source generates pulse bias power until the etching blocking layer is exposed to form a second opening. Due to the fact that the continuous bias power is utilized to form bias voltage for etching firstly, side wall appearance is good, and etching selection ratio to a photo layer is high. The continuous bias power is switched into pulse bias power to form bias voltage for etching in prior to exposure of the etching blocking layer, so that cuts are avoided from being formed at the side wall bottom, close to the etching blocking layer, of the to-be-etched material layer.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a semiconductor etching device and an etching method for a semiconductor structure. Background technique [0002] In the semiconductor manufacturing process, it is usually necessary to etch the semiconductor layer to form deep via holes. In order to effectively control the depth of the deep via hole, it is necessary to form an etch stop layer before forming the semiconductor layer. Using the etch stop layer as an etch stop layer is conducive to the formation of a via hole with a precise depth. The etch stop layer is generally made of insulating materials such as silicon oxide and silicon nitride. Since the aspect ratio of etched via holes has reached 10:1, or even more than 30:1, in order to ensure the economic feasibility of the manufacturing process, these processes must be carried out at a relatively high etching rate to ensure reasonable production capacity , but at the same time...

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Problems solved by technology

[0004] But the inventor found that please refer to figure 1 , the through hole 2 formed by the method will have a notch 1 (notching) at the position in contact with the etch barrier layer 3, and the notch 1 is located between the semiconductor layer 4 and the etch barrier layer 3, which will affect the etching The binding force between the final semiconductor layer 4 and the etch stop layer 3, and when other materials are subsequently filled in the through hole 2, the incision 1 may not be completely filled, and voids will be formed in the formed semiconductor structure. , will affect the electrical properties of the semiconductor structure

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