Formation method of semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: forming a first opening in a dielectric layer, the first opening spanning an adjacent gate structure; forming a first mask layer on the sidewall surface of the first opening, and the first mask layer The film layer spans the adjacent gate structure; a sacrificial layer filling the first opening is formed on the surface of the first mask layer, and the material etch resistance of the first mask layer is greater than the material etch resistance of the sacrificial layer; A second mask layer with a second opening is formed on the surface of the dielectric layer, the surface of the sacrificial layer and the surface of the first mask layer, and the second opening spans the sacrificial layer and the first mask layer; as a mask, etch the dielectric layer exposed by the sacrificial layer and the first mask layer along the second opening, and form discrete contact holes in the dielectric layer between adjacent gate structures; plug. The invention improves the position accuracy and shape accuracy of the side wall of the formed contact hole, thereby improving the performance of the formed semiconductor structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the continuous development of semiconductor process technology, such as the introduction of high-K gate dielectric layer, stress engineering technology, pocket ion implantation, and continuous optimization of materials and device structures, the size of semiconductor devices continues to shrink. However, when the feature size of the device is further reduced, planar transistors face huge challenges due to the more significant short-channel effect, process variation, and reduced reliability. Compared with planar transistors, FinFETs have fully depleted fins, lower dopant ion concentration fluctuations, higher carrier mobility enhancement, lower parasitic junction capacitance, and higher area usage efficiency has received extensive attention. [0003] In the integrated circuit m...

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Problems solved by technology

[0004] In the prior art, during the formation of the semiconductor structure, the size of the contact hole formed by the self-alignment process is likely to deviate from the design value, which will affect the connection performance of the formed conductive plug and affect the performance of the formed semiconductor structure

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