38 results about "Process alignment" patented technology

The present invention discloses an alignment device for alignment between a mask and a working table of a lithography machine, and can determine a basic alignment position by one time alignment with at least four marks. Compared with the prior art, the motion process required by the alignment of the mark is further reduced, thus further reducing the time cost of the alignment and improving the working efficiency of the system. Meanwhile, the present invention has a plurality of ways for processing alignment signals, can obtain different alignment accuracy, and can combine the further optimization of two aspects of the alignment accuracy and alignment efficiency by the selection of different processing strategies for the alignment signals based on the needs of users, and the detection of image quality can be realized.

The invention provides a project process workflow system based on plan templates aiming at problems existing in workflow technology, such as ''non compilation'' and so on. The invention also provides a corresponding method. The project process workflow system realizes an improvement for existing workflow system via a method of defining the typical plan templates according to a unit task formed bypacking work and corresponding workflow engine technology. The plan templates generate a progress schedule according to each specific project process, so as to drive the workflow. The invention can modify the progress schedule in the course of processing, namely realizing process adjustment in the course of processing the process. The invention makes the project process workflow system more flexible and more preciseness via technical means such as plan template technology, unit task technology and the corresponding workflow engine technology and so on. The invention also can satisfy requirements of running in the project process.

A method, apparatus and a system, for provided for performing an automated process flow adjustment. A semiconductor wafer is processed based upon a routing plan and a predetermined schedule. A fault detection relating to the processing of the semiconductor wafer is performed. Dynamically modifying the predetermined routing plan or the predetermined schedule based upon the fault detection. A predetermined process material delivery plan is dynamically modified based upon the modifying of the routing plan or modifying of the predetermined schedule.

The invention discloses a kind of system and method to automatically measure radio-frequency identification system, the system comprises: control panel, virtual terminal and load server. The method includes: run multiple virtual terminals simultaneously according to the tested system architecture on the load server, supports a wide range of environment, automatically calculate service response time, repeat load scenes easily, verify if the application process adjustment have a favourable impact on the service performance. Test the whole structure of application system, analyze problems and gives out solutions to help optimize application performance of middleware and information networks, used for RFID-based enterprise MES, CRM, ERP systems, or public information service platform for the public to inquire information. The present invention provides an ideal means of authentication before put on line, the virtual terminal simplify the difficulties of testing, improve test efficiency, simplifies configuration process through typical scenes and typical user behavior, and achieve computer-aided decision-making through automatic analysis of test card.

The invention discloses a part angle alignment method and a clamp thereof. The method comprises the steps that a process alignment block is firstly manufactured according to the structure of a part, a process alignment hole and mounting holes are machined in the process alignment block, and the process alignment hole or an angular straightening face is machined at the zero-degree position of the clamp; then the clamp is mounted on a machine tool, the process alignment hole or the angular straightening face on the clamp is aligned, the zero-degree angular position is set, and the clamp is pressed; the part is mounted on the clamp and pressed; then the process alignment block is mounted on the part through the process alignment hole and the mounting holes in the process alignment block; finally, a dial indicator is used for metering to straighten the angular straightening face on the clamp and align the alignment hole in the clamp to determine the zero-degree position, the process hole in the part or the process alignment hole in the process alignment block is aligned, the zero-degree angular position of the part is determined, and the zero-degree position of the machine tool is determined. The method is simple in operation process, reasonable in step and accurate in alignment, and by directly aligning an angular alignment locating hole in a locating block, the method is convenient to use and suitable for machining of batched parts.

The invention discloses a business flow control method, a method for requesting business processing, and corresponding devices and systems. The business flow control method comprises steps that a business processing request which is sent by a calling party and corresponds to a special business is received; through a level state machine pre-generated for the special business, a business flow of the special business is controlled; the level state machine comprises a main state machine and at least one sub state machine, the main state machine corresponds to a sub task sequence of the special business and comprises states corresponding to each sub task of the special business; the sub state machine corresponds to the sub tasks and comprises states corresponding to each operation link of the sub tasks. The method is advantaged in that the sub state machine corresponding to the sub tasks can be reused, flexibility of business flow adjustment is improved, system development and maintenance cost is reduced, and production capability and quality of a software system can be improved.

A number of modified lateral DMOS (LDMOS) transistor arrays are formed and tested to determine if a measured value, such as a series on-resistance, substrate current, breakdown voltage, and reliability, satisfies process alignment requirements. The modified LDMOS transistor arrays are similar to standard LDMOS transistor arrays such that the results of the modified LDMOS transistor arrays can be used to predict the results of the standard LDMOS transistor arrays.

The invention relates to an FOG process alignment method. The FOG process alignment method includes the steps of providing a glass panel with a first alignment mark; photographing the glass panel to generate first image information, and transmitting the first image information to an image processing module; generating second image information with a second alignment mark signal, and transmitting the second image information to the image processing module, wherein the first image information and the second image information are processed through the image processing module to be transmitted to a display module; displaying the image information received from the image processing module through the display module; adjusting the position and the size of a second alignment mark through an alignment mark control module to obtain new second image information, and displaying the new second image information through the display module; placing an FPC with a third alignment mark above the glass panel; photographing the FPC to generate third image information, and displaying the third image information through the display module; adjusting the position of the FPC so that the second alignment mark can be aligned with the third alignment mark. The FOG process alignment method is high in binding accuracy and high in product yield, and the production efficiency can be improved.

A business process (BP) adaptation system (400) includes a High-Variability enriched Goal Model (HVGM) (402) that captures and refines goals of a business process (BP) while modeling alternative options where the model captures non-functional or quality attributes used in an evaluation of a performance of the BP and an estimation of how various BP alternatives affect the quality attributes. The system further includes a High-Variability workflow-level / directly Executable Model (HVEM) (404), where the system is based on goal modeling and analysis for eliciting intentions behind a BP to achieve a desired goal and the HVGM explicitly models non-functional or quality concerns. The system can further include a semi-automatic generator (604) of BP metrics based on the quality attributes specified in the HVGM and a runtime infrastructure (610) where each deployed BP instance reflects a configuration selected for that instance in a corresponding portion of the HVGM.

The invention discloses an exposure method adopting a lithography machine. The method comprises the following steps executed in the continuous working process of the lithography machine: 101. ensuring silicon wafers to stand for a preset time on a silicon wafer carrying stage to ensure the temperature of the silicon wafers to be the same as the temperature of the silicon wafer carrying stage after the silicon wafers with a first temperature are transferred to the silicon wafer carrying stage with a second temperature; 102. opening vacuum equipment to ensure the silicon wafer carrying stage to attract the silicon wafers after silicon wafer deformation is completed; and 103. carrying out alignment and exposure operations. The method provided by the invention has the following beneficial effects that: the process alignment precision can be improved; high homogeneity between silicon wafers and between batches is realized in the continuous working process of the lithography machine; and the equipment utilization rate can be improved.

A laser process alignment measuring method applicable to a reel-to-reel manufacturing process including a laser process stage, wherein before at least one laser process stage, marks, patterns or surfaces (4,9) are made with printing ink on the base or carrier material of the web (2), and on which the laser beam used can make a mark (7, 10), for example, by removing or changing the printing ink, whereby at the laser process stage, another mark is plotted with the laser beam on the mark et al. printed with printing ink, and the position of the mark et al. printed with printing ink (4, 9) and the mark plotted with the laser (7, 10) are read optically to measure the alignment of the printing ink stage and the laser process stage.

The invention relates to the technical field of natural language processing, and specifically relates to a historical classics word segmentation method based on word alignment. The historical classics word segmentation method comprises following steps of firstly, carrying out word segmentation on the modern Chinese language in parallel corpora, splitting ancient Chinese prose word for word, and carrying out word alignment on the ancient Chinese prose and the modern Chinese language by means of an IBM Model 3 model; secondly, processing the alignment result obtained in the last step, and eliminating interference of punctuation marks and adverbs; thirdly, merging ancient words in dependence on the processed alignment result obtained in the last step; and finally, verifying words formed by three or more characters in the word segmentation result. According to the invention, on the premise that ancient Chinese tagged corpora are lacked, word segmentation of historical classics is effectively achieved; compared with a word segmentation method trained by modern Chinese tagged corpora, the historical classics word segmentation method based on word alignment is advantaged in that the word segmentation accuracy is greatly improved.

The invention provides a method for processing alignment mark measuring signals. The method comprises the following steps of: after sampling an alignment signal, fitting the signal by a fitting model to solve the best alignment position; performing model fitting by using a result acquired by light intensity sampling and position sampling; fitting the period of the signal while fitting model parameters so as to determine the phase of the signal; and finally solving and determining the best alignment position.

The invention belongs to the technical field of automobile manufacturing, and provides an assembly line performance evaluation method. The method comprises the following steps of, based on the total carbon emission, the time consumption and the assembly body production benefit of an assembly line, building a performance evaluation model of the assembly line; collecting evaluation parameters in anassembly process; inputting the evaluation parameters into the evaluation model to obtain assembly efficiency of the assembly line; and analyzing the assembly efficiency of the assembly line to obtainan evaluation result. According to the method disclosed by the invention, starting from the consumption of energy and time and the benefits of products, the input and output of the assembly line arefully considered, and the evaluation result of the whole assembly process is finally obtained; the operation condition of the assembly line can be reflected objectively, timely and accurately; and a scientific basis is provided for process adjustment of the assembly line.

The invention discloses a method for optimizing wafer exposure sequences. The method comprises the following steps: firstly, providing a to-be-exposed wafer; presetting a plurality of lens heating level values; detecting the current lens heating level value; and finally selecting an exposure path to expose the silicon wafer according to the current lens heating level value. According to the method for optimizing the wafer exposure sequences disclosed by the invention, different exposure sequences are selected according to the lens heating values; the movement of a slide holder is reduced; the lens heat effect is avoided; meanwhile, improvement of the capacity is taken into account; by virtue of the method for optimizing the wafer exposure sequence disclosed by the invention, a relatively good process alignment precision can be obtained; and the yield of a product is improved.

The invention discloses an alignment mark and its alignment method. The alignment mark includes a set of main marks formed on a semiconductor substrate, the main mark is composed of N groups of sub-marks, and the N groups of sub-marks Formed in N layers of film layers on the substrate, N is the number of layers that need to be aligned in this photolithography process; each group of sub-marks includes the first sub-mark in the horizontal direction and the second sub-mark in the vertical direction; the The first sub-marks are two groups of gratings in the horizontal direction, and the second sub-marks are two groups of gratings in the vertical direction. In this way, it can be aligned with multiple layers during alignment, thereby improving photolithographic precision and device yield.

The invention discloses an exposure method adopting a lithography machine. The method comprises the following steps of: 101. transferring silicon wafers to a silicon wafer carrying stage; 102. opening vacuum equipment to ensure the silicon wafer carrying stage to attract the silicon wafers; and 103. aligning the silicon wafers and exposing the chips on the silicon wafers in batches, wherein the chips are exposed at intervals in the exposure path during exposure of each batch. The method provided by the invention has the following beneficial effects that: the high temperature chips can be ensured to be cooled so that deformation can not be transferred to the adjacent chips; a better process alignment progress can be obtained; and high homogeneity between silicon wafers and between batches can be realized in the continuous working process of the lithography machine.

The invention discloses an array substrate, a liquid crystal display panel and a display device. Each sub-pixel comprises two sub-sub-pixels arranged in a second direction; and a switching transistorcorresponding to each sub-pixel is arranged between the two sub-sub-pixels and connected with the two sub-sub-pixels. Every two adjacent columns of sub-pixels in a first direction are used as one unitgroup; and any two adjacent unit groups are staggered by N sub-sub-pixels in the second direction. Therefore, for the overall array substrate, every two switching transistors are distributed uniformly in the second direction in each unit group. For a black matrix, one switching transistor needs to cover the widest part, so that the pocking mark feeling can be effectively improved by being compared with the prior art. Moreover, the grid lines correspondingly connected with each switching transistor are arranged between the two sub-sub-pixels in each sub-pixel; and thus in one sub-pixel, self compensating of the capacitance difference between the pixel electrode and the grid line caused by process alignment can be realized by utilizing the two sub-sub-pixels.

The invention discloses a self-alignment process for improving the performance of a safe working area of a gate-controlled power device. Before heavily doped P-type injection is carried out, a pad structure is formed in the direction of a gate end toward an emitter contact hole, and then the pad structure is used as a barrier for heavily doped P-type injection. After heavily doped P-type injectionis carried out, the pad structure is removed. According to the invention, the width of the pad structure can be adjusted by adjusting process parameters such as deposition time of a nitride layer, gas flow rate and pressure, so as to shorten the distance between a heavily doped P-type area and a gate to within 1 micron; the performance of the safe working area of the gate-controlled power deviceis greatly improved; the pad structure is used as the barrier; self-alignment of heavily doped P-type injection can be realized without the barrier of a photoresist; the influence of the deviation ofphotolithography process alignment between the emitter contact hole and the gate on the device is fundamentally eliminated; and the process provided by the invention is simple, and is conductive to improving the performance consistency of the device.

The invention provides a method for adjusting a service flow in open architecture and is applied to network equipment. The network equipment comprises an open application architecture (OAA) board and a main control board, the OAA board comprises an OAA front insertion board and a forwarding rear insertion board; and the OAA front insertion board is used for performing OAA processing on a received message. The method comprises the following steps of: A, detecting whether a single board inserted into the network equipment is an OAA board; and B, after the OAA board is inserted into the network equipment, transmitting a backflow rule of the current board to the OAA front insertion board through a control channel between the main control board and the OAA board, wherein the backflow rule of the current board is used for sending a message processed by the OAA front insertion board to the forwarding rear insertion plate to be processed through an inter-board communication mechanism. By the method, resources on the existing forwarding rear insertion board on the OAA board are well used, and the network equipment does not need an extra OAA proxy board, so that the manufacturing cost of the network equipment is greatly reduced; and moreover, the message processing flow is simplified.

The invention relates to an FOG process alignment method. The FOG process alignment method includes the steps of providing a glass panel with a first alignment mark; photographing the glass panel to generate first image information, and transmitting the first image information to an image processing module; generating second image information with a second alignment mark signal, and transmitting the second image information to the image processing module, wherein the first image information and the second image information are processed through the image processing module to be transmitted to a display module; displaying the image information received from the image processing module through the display module; adjusting the position and the size of a second alignment mark through an alignment mark control module to obtain new second image information, and displaying the new second image information through the display module; placing an FPC with a third alignment mark above the glass panel; photographing the FPC to generate third image information, and displaying the third image information through the display module; adjusting the position of the FPC so that the second alignment mark can be aligned with the third alignment mark. The FOG process alignment method is high in binding accuracy and high in product yield, and the production efficiency can be improved.

The invention discloses a photoetching alignment method used in a manufacturing process of a semiconductor device. When a process alignment layer or a photoetching alignment mark is not clear while a base layer has a photoetching alignment mark with a concave-convex type step structure, the process alignment layer is subjected to photoetching alignment; the photoetching alignment method used in manufacturing of the semiconductor device comprises a step of forming secondary alignment marks on the process alignment layer after the process alignment layer is formed on the base layer and before the process alignment layer is subjected to photoresist uniformization. By adoption of the photoetching alignment method, the technical problem of difficulty in identifying unclear marks in exposure of many layers caused by complex structure of the semiconductor device in the manufacturing process of the existing semiconductor device can be solved; mark signals with steps and hard to identify can be optimized; and in addition, the execution steps are simple and easy to implement.

The invention discloses a photoetching alignment method used in a manufacturing process of a semiconductor device. When a process alignment layer or a photoetching alignment mark is not clear while a base layer has a photoetching alignment mark with a concave-convex type step structure, the process alignment layer is subjected to photoetching alignment; the photoetching alignment method used in manufacturing of the semiconductor device comprises a step of forming secondary alignment marks on the process alignment layer after the process alignment layer is formed on the base layer and before the process alignment layer is subjected to photoresist uniformization. By adoption of the photoetching alignment method, the technical problem of difficulty in identifying unclear marks in exposure of many layers caused by complex structure of the semiconductor device in the manufacturing process of the existing semiconductor device can be solved; mark signals with steps and hard to identify can be optimized; and in addition, the execution steps are simple and easy to implement.

The invention discloses a wafer object table temperature control system of a lithography machine and a control method thereof. The temperature control system comprises a silicon wafer object table, a mask plate and a lithography machine light source, as well as a temperature measurement device with a temperature sensor, an element and a computing control system; a silicon wafer holding area and a temperature measurement area are arranged on the silicon wafer object table; the silicon wafer holding area is located at the front end of the temperature measurement area; the temperature measurement device with the temperature sensor is arranged in the temperature measurement area; the element is located between the lithography machine light source and the mask plate; and the temperature measurement device, the computing control system and the element are connected in series to form a temperature control loop. Through the temperature control system and the control method thereof, the temperature of a silicon wafer during exposure can be controlled, which is beneficial to prevent the deformation of the silicon wafer caused by the temperature, so that better process alignment precision can be obtained and high uniformity among silicon wafers and batches during the continuous service of the lithography machine can be realized.

The invention discloses a wafer object table temperature control system of a lithography machine and a control method thereof. The temperature control system comprises a silicon wafer object table, a mask plate and a lithography machine light source, as well as a temperature measurement device with a temperature sensor, an element and a computing control system; a silicon wafer holding area and a temperature measurement area are arranged on the silicon wafer object table; the silicon wafer holding area is located at the front end of the temperature measurement area; the temperature measurement device with the temperature sensor is arranged in the temperature measurement area; the element is located between the lithography machine light source and the mask plate; and the temperature measurement device, the computing control system and the element are connected in series to form a temperature control loop. Through the temperature control system and the control method thereof, the temperature of a silicon wafer during exposure can be controlled, which is beneficial to prevent the deformation of the silicon wafer caused by the temperature, so that better process alignment precision can be obtained and high uniformity among silicon wafers and batches during the continuous service of the lithography machine can be realized.

A method of forming measuring targets for measuring the dimensions of a substrate during a substrate manufacturing process is provided. First, a board having a base layer and a conductive layer is provided, wherein the conductive layer is disposed on a surface of the base layer. Then, at least one through hole is formed in the board as a measuring target for measuring the dimensions of the substrate. Next, a plated via is formed in the through hole as another measuring target for measuring the dimensions of the substrate. Thereafter, a patterned dielectric layer is formed on the board to expose the plated via as a next measuring target for measuring the dimensions of the substrate. In the present invention, measuring targets are formed during a substrate manufacturing process and the dimensions of the substrate are measured instantly. The accuracy in process alignment is improved without increasing the fabrication cost.