The invention relates to a multi-chip integrated stacked sandwiched packaging structure and a technological method therefor. The technological method comprises the following steps of step 1, providing a first lead frame; step 2, coating the first lead frame with solder paste; step 3, implanting a first chip into the first lead frame solder paste; step 4, providing a second lead frame; step 5, coating the second lead frame with the solder paste; step 6, enabling the first chip to be laminated by the second lead frame; step 7, performing reflow soldering; step 8, coating the second lead frame with the solder paste; step 9, implanting a second chip into the second lead frame solder paste; step 10, providing a third lead frame; step 11, coating the third lead frame with the solder paste; step 12, enabling the second chip to be laminated by the third lead frame; step 13, performing reflow soldering; step 14, performing plastic package by a plastic package material; and step 15, performing a cutting or punching operation. The technological method has the beneficial effects that the thermal dissipation capability of products is improved, and the packaging resistance of the products is lowered.