Multi-chip integrated stacked sandwiched packaging structure and technological method therefor

Abstract

The invention relates to a multi-chip integrated stacked sandwiched packaging structure and a technological method therefor. The technological method comprises the following steps of step 1, providing a first lead frame; step 2, coating the first lead frame with solder paste; step 3, implanting a first chip into the first lead frame solder paste; step 4, providing a second lead frame; step 5, coating the second lead frame with the solder paste; step 6, enabling the first chip to be laminated by the second lead frame; step 7, performing reflow soldering; step 8, coating the second lead frame with the solder paste; step 9, implanting a second chip into the second lead frame solder paste; step 10, providing a third lead frame; step 11, coating the third lead frame with the solder paste; step 12, enabling the second chip to be laminated by the third lead frame; step 13, performing reflow soldering; step 14, performing plastic package by a plastic package material; and step 15, performing a cutting or punching operation. The technological method has the beneficial effects that the thermal dissipation capability of products is improved, and the packaging resistance of the products is lowered.

Description

technical field [0001] The invention relates to a multi-chip stacked sandwich package structure and a process method thereof, which belong to the technical field of semiconductor packaging. Background technique [0002] In recent years, with the continuous pursuit of power density in electronic products, whether it is Diode (secondary tube) or Transistor (transistor) packaging, especially the MOS products in Transistor are moving towards higher power, smaller size, faster , The trend of better heat dissipation is developing. The one-time manufacturing method of packaging is also gradually sprinting and challenging from single-chip packaging technology to high-density, high-difficulty and low-cost one-time packaging technology in small areas or even larger areas. [0003] Therefore, the packaging of MOS products has been improved in terms of various electrical properties such as parasitic resistance, capacitance, and inductance, packaging structure, heat dissipation capabili...

AI Technical Summary

Problems solved by technology

[0013] 1.) In this MOS package structure, the drain, source and gate of the chip and the lead frame are connected to each other by using different equipment, the process is complicated, and the purchase cost of the equipment is high

[0014] 2.) When this MOS packaging structure couples the metal splint and the metal bonding wire to the chip and the pin, it can only be carried out one by one, and the whole piece cannot be integrally formed, and the manufacturing efficiency is low.

[0015] 3.) The internal and external pins of this MOS package are not integrally formed, but welded by solder, so there is still a high contact resistance at the junction of the internal and external pins (that is, the contact between the metal splint, the metal strip and the lead frame)

[0016] 4.) When using a metal splint to couple to the chip and the metal pin, because of the different chip board or chip area, the metal splint and the punching and handling mold and mechanism of the metal splint must be redesigned and redesigned. Manufacturing, and these changes often result in waste of acquisition money, waste of re-architecting time costs, waste of business opportunity costs, and waste of staffing

[0017] 5.) When using a metal splint to couple to the chip and metal pins, because the metal splint is very small, during the production punching, handling and welding process, the metal splint often falls during transportation, falls during welding, and poor welding. Damage to yield and reliability

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