Multi-chip and multi-shingle stacked sandwich package structure with exposed frames and technique of multi-chip and multi-shingle stacked sandwich package structure

Abstract

The invention relates to a multi-chip and multi-shingle stacked sandwich package structure with exposed frames and a technique of the multi-chip and multi-shingle stacked sandwich package structure. The method comprises the following steps: (1) providing a first lead frame; (2) coating the first lead frame with a tin paste; (3) implanting a first chip into the tin paste of the first lead frame; (4) providing a second lead frame, coating the second lead frame with the tin paste; (5) laminating the second lead frame on the first chip; (6) carrying out reflow soldering; (7) coating the second lead frame with the tin paste; (8) implanting a second chip into the second lead frame; (9) providing a third lead frame, coating the third lead frame with the tin paste; (10) laminating the third lead frame on the second chip; (11) carrying out reflow soldering; (12) carrying out plastic packaging with a molding compound; and (13) carrying out a cutting or punching operation. The multi-chip and multi-shingle stacked sandwich package structure with the exposed frames have the beneficial effects that the heat dissipating ability of a product is increased; and the package resistance of the product is reduced.

Description

technical field [0001] The invention relates to a frame-exposed multi-chip multi-lap stacked sandwich packaging structure and a process method thereof, belonging to the technical field of semiconductor packaging. Background technique [0002] In recent years, with the continuous pursuit of power density in electronic products, whether it is Diode (secondary tube) or Transistor (transistor) packaging, especially the MOS products in Transistor are moving towards higher power, smaller size, faster , The trend of better heat dissipation is developing. The one-time manufacturing method of packaging is also gradually sprinting and challenging from single-chip packaging technology to high-density, high-difficulty and low-cost one-time packaging technology in small areas or even larger areas. [0003] Therefore, the packaging of MOS products has been improved in terms of various electrical properties such as parasitic resistance, capacitance, and inductance, packaging structure, he...

AI Technical Summary

Problems solved by technology

This MOS packaging structure replaces the bonding wires in the traditional MOS packaging with metal splints, which reduces part of the packaging resistance, but there are still the following defects: First, the drain, source and gate of the chip in this MOS packaging structure are formed with the lead frame. Different devices are required for interconnection, the manufacturing process is complicated, and the purchase cost of the devices is high; secondly, when the metal splint and metal bonding wires are coupled to the chips and pins in this MOS packaging structure, it can only be done one by one. It cannot be integrally formed in one piece, and the manufacturing efficiency is low

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