239results about How to "Good coplanarity" patented technology

Provided are a semiconductor flip chip package with warpage control and fabrication methods for such packages. The packages of the present invention include heat spreader lids that are rigidly attached to the die or packaging substrate with a bond that can withstand the considerable bowing pressures caused by the CTE mismatch between the die and substrate. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the PCB board to which it is ultimately bound. Package reliability is thereby also enhanced, particularly for large die sizes.

In one embodiment of the present invention, there is provided a semiconductor device including a first semiconductor element mounted, through flip-chip bonding, on the element mounting surface of a first wiring substrate, and a resin layer that coats substantially the entire element mounting surface of the first wiring substrate. The first semiconductor element has two opposite surfaces. One surface faces the element mounting surface of the first wiring substrate, and the other surface is not coated by the resin layer.

A chip embedded package structure is provided. A stiffener is disposed on a tape. The tape has at least an alignment mark and the stiffener has at least a chip opening. A chip having a plurality of bonding pads thereon is disposed on the tape within the chip opening such that the bonding pads face the tape. A plurality of through holes is formed in the tape to expose the bonding pads respectively. After that, an electrically conductive material is deposited to fill the through holes and form a plurality of conductive vias that connects with the bonding pads respectively. A multi-layered interconnection structure is formed on the surface of the tape away from the chip. The multi-layered interconnection structure has an inner circuit that connects to the conductive vias. The inner circuit has a plurality of metallic pads disposed on the outer surface of the multi-layered interconnection structure.

A method for forming a raised source and drain structure without using selective epitaxial silicon growth. A semiconductor substrate is provided having one or more gate areas covered by dielectric structures. Doped polysilicon structures are adjacent to the dielectric structures on each side and are co-planar with the dielectric structures from a CMP process. The first dielectric structures are removed to form gate openings and a liner oxide layer is formed on the bottom and sidewalls of the gate openings. Dielectric spacers are formed on the liner oxide layer over the sidewalls of the gate openings, and the liner oxide layer is removed from the bottom of the gate openings and from over the doped polysilicon structures. Source and drain regions are formed in the semiconductor substrate by diffusing impurity ions from the doped polysilicon layer. A gate oxide layer and a gate polysilicon layer are formed over the semiconductor structure and the gate polysilicon layer is planarized to form a gate electrode. In a key step, the dielectric spacers are removed to form spacer openings, and impurity ions are implanted through the spacer openings and annealed to form source and drain extensions. The dielectric spacers are reformed and a self-aligned silicide layer is formed on the doped polysilicon structure and the gate electrode. Alternatively, the self-aligned silicide layer can be formed prior to removing the dielectric spacers and implanting ions to form source and drain extensions.

Embodiments of the present invention provide a wiring substrate that includes a structure where a plurality of projection electrodes are arranged within an electrode formation region on a substrate main surface. At least one among the plurality of projection electrodes has a larger outer diameter than an outer diameter of a via conductor and is a variant projection electrode which has a roughened upper surface. Embodiments of the present invention also provide methods for manufacturing wiring substrates having one or more of said variant projection electrode.

The invention relates to near infrared fluoro-boron dipyrrole fluorescent dyes and a synthesis method of the fluorescent dyes. The dyes have the general formula shown in the specification. The fluorescent dyes are synthesized from aldehyde or imine compounds of halogenated pyrrole or isoindazole and pyrrole derivatives by a one-pot method. The emission wavelength of the fluorescent dyes is more than 600nm, and the emission spectra of the monostyryl-substituted dyes and derivatives thereof can be up to 714nm. The fluorescent dyes have excellent light, physical and chemical performances of higher fluorescent quantum yield (0.61-0.91) and better light stability and the like, and has excellent application prospects in fluorescence labeling, biological imaging and other bioanalysis fields.

A singulation method used in leadless packaging process is disclosed. An array of molded products on an upper surface of a lead frame is utilized in the singulation method. The lead frame has a plurality of dambars between the molded products. The lower surface of the lead frame is attached with a tape. Each of the molded products includes a semiconductor chip encapsulated in a package body and electrically coupled to the upper surface of the lead frame. The singulation method is accomplished by etching the upper surface of the lead frame with the package bodies as mask until each dambar is etched away.

The invention discloses a novel organic electroluminescence device. The device comprises a first electrode, a second electrode and one or more layers of organic layers between the first electrode andthe second electrode. Each organic layer at least comprises a light emitting layer and an electronic transmission layer. The device is characterized in that the thickness of each electronic transmission layer is 5-100nm; each electronic transmission layer comprises at least one kind of compound shown by the formula (I) shown in the description, wherein L is selected from a chemical bond, an arylidene or sub-polycyclic aromatic hydrocarbon group of C6-C12, and a sub-heteroaryl or sub-polycyclic heteroaryl aromatic hydrocarbon group of C3-C12; the Ar1, the Ar2 and the Ar3 are respectively selected from the substituted or non-substituted aryl or polycyclic aromatic hydrocarbon group of C6-C30, and the substituted or non-substituted heteroaryl group or polycyclic heteroaryl aromatic hydrocarbon group of C3-C30; the R1, the R2, the R3 and the R4 are selected from hydrogen, the alkylene of C1-C10, the halogen, the cyan, the nitryl, the substituted or non-substituted aryl or polycyclic aromatic hydrocarbon group of C6-C30, and the substituted or non-substituted heteroaryl group or polycyclic heteroaryl aromatic hydrocarbon group of C3-C30; and the R3 can be connected with the R4, so an annular structure can be formed. According to the invention, the device is advantaged by low working voltage and high light emitting efficiency.

The invention discloses a core column component of a winding type pasted electronic element and a manufacturing method of the core column component. The core column component comprises a core column and an external electrode, wherein the core column comprises a left-end convex part, a right-end convex part and a core column body which is connected with the left-end and right-end convex parts, grooves are arranged on both the left-end and right-end convex parts, and the external electrode continuously covers the upper surfaces of the left-end and right-end convex parts and the surface of the groove. The method of the invention is used for manufacturing the core column component. By means of the core column component of the invention, coil ends with various wire diameters can be conveniently welded without increasing the overall height of the product.

An electronic device manufacturing method includes: setting a solder material on electrodes of a first circuit assembly; setting a resin having a flux action on one surface of a second circuit assembly so as to entirely cover solder bumps formed on the one surface of the second circuit assembly; setting the second circuit assembly on the first circuit assembly via the resin so that the solder material set on the electrodes of the first circuit assembly and the solder bumps of the second circuit assembly are put into contact with each other; and applying thermal energy to connecting portions between the solder material and the solder bumps and to the resin. By carrying out these processes, an electronic device in which the first circuit assembly and the second circuit assembly are joined together and in which their junction portions are sealed by the resin is manufactured. As a result, in the electronic device, junction reliability can be improved.

The invention discloses an electroplating solution composition capable of being used for improving salient point coplanarity. The electroplating solution composition comprises a leveling agent which is polymer with positive electricity, wherein a polymeric monomer of the polymer comprises the following monomer structure: FORMULA as shown in the specification, wherein R1 on N is selected from alkyls of C1-4, and R2 on the N is selected from the alkyls of C1-4. During high-speed electroplating (2.5 mu m/min), the electroplating solution composition provided by the invention still can keep relatively good plating coplanarity which is much smaller than an industrial required value by 3%; the plating is flat in feature, can be used for copper pillar salient point electroplating of a 3D interconnecting and packaging process, and has a good market prospect.

The objectives of the present invention include to mount an electric contact or an electric connector on a printed circuit board without conducting the soldering work, and to make mounting the electric contact on a printed circuit board by an automatic machine even when the electric contact is microminiaturized. The electric contact using resin solder according to the present invention is connected to a printed circuit board, which has a conductor being provided on a surface thereof. This electric contact comprises a leg, which contacts the conductor of the printed circuit board, and a connecting part, which is connected to the conductor of the counterpart member. At least a part of the leg, which contacts the conductor of the printed circuit board, is made of a lead-free ultrahigh-conductive plastic being a conductive resin composite. The electric connector comprises the electric contact and an insulating housing, which holds the electric contact so that the part of the leg, which contacts the conductor of the printed circuit board, is exposed.

The invention discloses a special fixture for gold removal and tin coating for QFN encapsulated components, and a method for gold removal and tin coating. The special fixture is composed of a cross brace, a rail seat, a bottom frame, an upper supporting plate, a component supporting plate, a fastener, a press sheet, a long screw rod, a short screw rod, a component screw rod, a bearing seat, a cotter pin and a wheel shaft, wherein the cross brace and the rail seat form a guide rail; the wheel shaft, the bearing seat and the bottom frame are assembled into a lower supporting mechanism capable of moving on the guide rail; the upper supporting plate is fixed on the bottom frame, the component supporting plate is placed in a groove of the upper supporting plate, and the components are placed in installation hole positions of the component supporting plate; and the guide rail of the special fixture is horizontally placed on the table surface of a repair workbench for through-hole components, and the lower supporting mechanism is moved to enable bonding pads of the QFN components to complete gold removal and tin coating through the wave crests of a spewing molten tin-lead alloy. The method disclosed by the invention is high in applicability, and can be used for gold removal and tin coating for all the QFN components on the repair workbench for through-hole components.

The invention discloses a weld-leg internally-installed surface-mounted elastic key and a manufacturing method thereof. The key comprises a base and a key soft body. The key soft body comprises a key convex body, an elastic soft main body and a conductive contact. The elastic soft main body is in a conical cylinder shape, the small-opening inner edge of the elastic soft main body is connected with the key convex body, the large opening end of the elastic soft main body is connected with the upper surface of the base, and a through hole corresponding to the large opening end of the elastic soft main body in size is formed in the middle of the base; the conductive contact is arranged on the lower end face of the key convex body; protruding-downwards weld legs are arranged on the bottom end face of the base and are not exposed out of the outer side of the base, and the lower end faces and the periphery faces of the weld legs are the weld faces. A key lead is good in coplanarity, and the requirements of the size, the shape and the number of the different key leads can be met; the weld-leg internally-installed surface-mounted elastic key is applied to surface mounting application, and has the advantages of being low in manufacturing cost and good in practicability; by means of the key, gapless arrangement can be achieved, and particularly, the key has the prominent advantages in high-density product application occasions and high-integration-density product application occasions.