1642 results about "Solder material" patented technology

A method of constructing a backside illuminated image sensor is described. The method includes the steps of forming a semiconductor wafer, forming at least electrical contacts in the semiconductor wafer, forming, in a handle wafer separate from the semiconductor wafer, a plurality of via holes, attaching the semiconductor wafer to the handle wafer such that the via holes in the handle wafer are aligned with the respective electrical contacts on the semiconductor wafer, removing the substrate layer from the semiconductor wafer, removing at least a portion of the handle wafer to expose the plurality of via holes, filling each of the exposed via holes with a conductive material and applying a solder material to each of the exposed via holes such that the conductive material in each of the via holes is electrically connected to the solder material.

A circuit board assembly with a substrate having a laminate construction of ceramic layers, such as an LTCC ceramic substrate. The substrate is configured for the purpose of improving the thermal management of power circuit devices mounted to the substrate. Thermally-conductive vias extend through the substrate from a first surface thereof to a second surface thereof. A circuit device is mounted to the first surface of the substrate and is electrically interconnected to conductor lines of the substrate. The device is also thermally coupled to the thermally-conductive vias with a first solder material. A heat sink located adjacent the second surface of the substrate is bonded to the thermally-conductive vias with a second solder material, such that the first solder material, the thermally-conductive vias, and the second solder material define a thermal path from the device to the heat sink.

Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the invention is directed toward a method for manufacturing a microelectronic workpiece having a plurality of microelectronic dies. The individual dies include an integrated circuit and a terminal electrically coupled to the integrated circuit. In one embodiment, the method includes forming an opening in the workpiece in alignment with the terminal. The opening can be a through-hole extending through the workpiece or a blind hole that extends only partially through the substrate. The method continues by constructing an electrically conductive interconnect in the workpiece by depositing a solder material into at least a portion of the opening and in electrical contact with the terminal. In embodiments that include forming a blind hole, the workpiece can be thinned either before or after forming the hole.

A pre-solder structure on a semiconductor package substrate and a method for fabricating the same are proposed. A plurality of conductive pads are formed on the substrate, and a protective layer having a plurality of openings for exposing the conductive pads is formed over the substrate. A conductive seed layer is deposited over the protective layer and openings. A patterned resist layer is formed on the seed layer and has openings corresponding in position to the conductive pads. A plurality of conductive pillars and a solder material are deposited in sequence in each of the openings. The resist layer and the seed layer not covered by the conductive pillars and the solder material are removed. The solder material is subject to a reflow-soldering process to form pre-solder bumps covering the conductive pillars.

A light emitting device includes a light-emitting portion including a metal part including a metal able to be bonded to a solder material, and a heat dissipation member that includes aluminum, aluminum alloy, magnesium or magnesium alloy and a bonding portion processed to be bonded to the solder material. The metal part of the light-emitting portion is bonded via the solder material to the bonding portion of the heat dissipation member. The solder material includes a material unable to be directly bonded to the heat dissipation member, the metal part of the light-emitting portion is formed by metalizing an insulation of ceramic or semiconductor, and the bonding portion includes a thermal expansion coefficient between that of the heat dissipation member and that of the insulation.

A bump structure of a semiconductor package and a method for fabricating the same are provided. The bump structure is used to connect a semiconductor element to a carrier of the semiconductor package. The fabrication method primarily employs an electroplating process to form the bump structure including an under bump metallurgy (UBM) layer, at least one I-shaped conductive pillar, and a solder material. This allows fine-pitch electrical connection pads to be arranged in the semiconductor package, and also provides an enhanced support structure and a sufficient height between the semiconductor element and the carrier.

A bonded member including a ceramic base material 1 and a metallic member 7 which are bonded together, wherein a solder material 5 comprising Au is disposed on the surface of the ceramic base material 1 via an active metal layer, the active metal layer and the solder material 5 are molten by heating so as to form a precoat layer 6, the metallic member 7 is disposed on the surface of the precoat layer 6 via an insertion metal layer comprising pure metal which may form an alloy having a lower melting point than Au with Au or an alloy of the pure metal and Au, and the insertion metal layer and at least a portion in the vicinity of the interface between the insertion metal layer and the precoat layer 6 are molten by heating to bond the metallic member 7 and the precoat layer 6.

A first level packaging assembly includes a chip-mounting base defined by a first surface and a second surface opposite to the first surface; a plurality of external connection lands disposed on the first surface; a plurality of solder balls connected to the external connection lands; a plurality of internal connection lands disposed on the second surface; a plurality of solder joints connected to the internal connection lands including solder materials having lower melting temperature than the solder balls; a semiconductor chip defined by a third surface and a fourth surface opposite to the third surface, connected to the solder joints on the third surface; and an underfill resin sandwiched between the second and third surfaces so as to mold the solder joints.

When a friction stir weld tool penetrates the interface of two workpieces of dissimilar metal alloy materials, the resultant weld of the different alloy materials may produce a weak weld joint. Such weak joints are often experienced, for example, when attempting to form spot welds or other friction stir welds between a magnesium alloy sheet or strip and an aluminum alloy sheet or strip. It is discovered that suitable coating compositions placed at the interface of assembled workpieces can alter the composition of the friction stir weld material and strengthen the resulting bond. In the example of friction stir welds between magnesium alloy and aluminum alloy workpieces, it is found that combinations of copper, tin, and zinc, and other powders can strengthen the magnesium-containing and aluminum-containing friction stir weld material.

Methods of assembly for a semiconductor light emitting device package may include positioning a submount on a mounting substrate with a solder material and a flux therebetween. The semiconductor light emitting device is positioned on a top side of the submount with a solder material and a flux therebetween to provide an assembled stack that has not been reflowed. The assembled stack is reflowed to attach the submount to the mounting substrate and the light emitting device to the submount.

A method of using coated and/or magnetic particles to deposit structures including solder joints, bumps, vias, bond rings, and the like. The particles may be coated with a solderable material. For solder joints, after reflow the solder material may comprise unmelted particles in a matrix, thereby increasing the strength of the joint and decreasing the pitch of an array of joints. The particle and coating may form a higher melting point alloy, permitting multiple subsequent reflow steps. The particles and/or the coating may be magnetic. External magnetic fields may be applied during deposition to precisely control the particle loading and deposition location. Elements with incompatible electropotentials may thereby be electrodeposited in a single step. Using such fields permits the fill of high aspect ratio structures such as vias without requiring complete seed metallization of the structure. Also, a catalyst consisting of a magnetic particle coated with a catalytic material, optionally including an intermediate layer.

Methods of assembly for a semiconductor light emitting device package may include positioning a submount on a mounting substrate with a flux material therebetween and at least substantially free of solder material therebetween. The submount has a metal bonding layer facing the mounting substrate. A semiconductor light emitting device is positioned on a top side of the submount with a flux material therebetween to provide an assembled stack. The assembled stack is reflowed to attach the metal bonding layer of the submount to the mounting substrate and to attach the light emitting device to the submount.

Techniques for utilizing a bonding agent that allows a solder reflow process to occur at a lower reflow temperature. One area of use includes semiconductor device manufacturing processes. The bonding agent is placed between a solder ball and a contact surface. The bonding agent has a melting temperature that is lower than that of the solder ball. Reflow is then performed at a relative low temperature that is high enough for reflowing the bonding agent, yet at the same time, lower than what would be necessary to reflow the solder material. Since, the electrical system is not subjected to the high temperatures necessary for reflowing the solder material, the electronic system experiences less high-temperature related damage.

An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint.

There is provided an improved lead-free solder material which is preferably used as a connecting material in a mounting process of an electronic component. The solder material according to the present invention contains 1.0 to 4.0% by weight of Ag, 1.0 to 20% by weight of Bi, 0.1 to 1.0% by weight of Ni, and 75 to 97.9% by weight of Sn.

A cooling apparatus and method of fabrication are provided for facilitating removal of heat from a heat-generating electronic device. The method of fabrication includes: obtaining a solder material; disposing the solder material on a surface to be cooled; and reflowing and shaping the solder material disposed on the surface to be cooled to configure the solder material as a base with a plurality of fins extending therefrom. In addition to being in situ-configured on the surface to be cooled, the base is simultaneously metallurgically bonded to the surface to be cooled. The solder material, configured as the base with a plurality of fins extending therefrom, is a single, monolithic structure thermally attached to the surface to be cooled via the metallurgical bonding thereof to the surface to be cooled.

A method of forming integrated circuit (IC) die configured for attachment to another die or a package substrate, and stacked IC devices therefrom. At least one IC die having a top semiconductor surface and a bottom surface and at least one through substrate via (TSV) including a tip protruding beyond the bottom surface to a tip length is provided. The tip has an outer dielectric tip liner, and an electrically conductive portion within the outer dielectric tip liner. A compliant layer is applied to the bottom surface of the IC die. The dielectric tip liner is removed from a distal portion of the tip to expose an electrically conductive tip portion. A solder material is deposited on the exposed distal portion of the tip. The solder material is reflowed and coalesced to form a solder bump on the distal portion of the tip.

Described is a method of forming a solder deposit on a substrate comprising the following steps i) provide a substrate including a surface bearing electrical circuitry that includes at least one contact area, ii) form a solder mask layer that is placed on the substrate surface and patterned to expose the at least one contact area, iii) contact the entire substrate area including the solder mask layer and the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface, iv) electroplate a solder deposit layer containing a tin or tin alloy onto the conductive layer and v) etch away an amount of the solder deposit layer containing tin or tin alloy sufficient to remove the solder deposit layer from the solder mask layer area leaving a solder material layer on the at least one contact area.

A mask (110; see also 160, 210, 260, 310, 408, 500, 702, 802, 904) having a plurality of openings (cells) is disposed on, or nearly on, the surface of a substrate (102), the openings (112) of the mask being aligned over a corresponding plurality of pads (104) on the substrate. The openings in the mask are filled with solder material (114). A pressure plate (120) is disposed over the mask to capture the solder material in the cells. Heat is directed at the mask (through the pressure plate) to reflow the solder. This is done in an inverted or partially inverted orientation. The stackup (assembly) of substrate/mask/pressure plate may be un-inverted prior to cooling. Mask configurations, methods of mounting the masks, and solder material compositions are described. The methods are robust, and are well suited to fine pitch as well as coarse pitch ball bumping of substrates.