Electroplating solution composition capable of being used for improving salient point coplanarity

Abstract

The invention discloses an electroplating solution composition capable of being used for improving salient point coplanarity. The electroplating solution composition comprises a leveling agent which is polymer with positive electricity, wherein a polymeric monomer of the polymer comprises the following monomer structure: FORMULA as shown in the specification, wherein R1 on N is selected from alkyls of C1-4, and R2 on the N is selected from the alkyls of C1-4. During high-speed electroplating (2.5 mu m / min), the electroplating solution composition provided by the invention still can keep relatively good plating coplanarity which is much smaller than an industrial required value by 3%; the plating is flat in feature, can be used for copper pillar salient point electroplating of a 3D interconnecting and packaging process, and has a good market prospect.

Description

technical field [0001] The invention belongs to the field of semiconductor chip packaging, and relates to a copper bump electroplating process for 3D interconnection packaging, in particular to an additive for improving the coplanarity of bumps. Background technique [0002] The traditional interconnection process technology of semiconductor chips is a thin film process of aluminum process. However, when the line width is less than 0.18um, reliability problems such as signal delay and electromigration seriously affect the reliability of integrated circuits. In 1999, IBM took the lead in developing the damascenes chip copper interconnection process, and achieved mass production of the chip copper interconnection process in 2000. Copper metal is considered to be an excellent chip interconnection material due to its excellent electrical conductivity, thermal conductivity, low melting point and easy extension. As the feature size of the chip line width is getting smaller and s...

AI Technical Summary

Problems solved by technology

As the feature size of the chip line width is getting smaller and smaller, the number of I / Os of the chip is increasing, and the traditional packaging method can no longer meet the requirements. An advanced wafer 3D interconnection packaging technology (WLP) came into being.

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