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Alignment marker and alignment method thereof

A technology for aligning marks and markings, applied to electrical components, electrical solid devices, circuits, etc., can solve problems affecting lithography accuracy and device yield, and can not take into account the alignment effect, so as to improve lithography accuracy and device yield rate effect

Active Publication Date: 2015-09-30
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this does not take into account the alignment effect with the multilayer structure, which affects the lithography accuracy and device yield

Method used

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  • Alignment marker and alignment method thereof
  • Alignment marker and alignment method thereof
  • Alignment marker and alignment method thereof

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Embodiment Construction

[0022] The core idea of ​​the present invention is to provide an alignment mark and its alignment method. The alignment mark is composed of multiple groups of sub-marks formed in different layers. The main mark composed of the multiple groups of sub-marks is the same as the standard Scribe main mark (SPM) has the same structure, and the standard alignment method can be used to align with the multi-layer structure at one time, so that it can be aligned with multiple layers at the same time.

[0023] The alignment mark and its alignment method proposed by the present invention will be further described in detail below with reference to the drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that the drawings are all in a very simplified form and use imprecise ratios, which are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the ...

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Abstract

The present invention discloses an alignment marker and alignment method thereof. The alignment marker comprises a group of main markers formed on a semiconductor substrate. Each of the main markers is formed by N groups of sub markers which are formed in the N layers of films on the substrate, and N is the number of layers which are needed to be aligned in lithographic process. Each group of the sub markers comprises a first sub marker of a horizontal direction and a second sub marker of a vertical direction. The first sub marker is two groups of gratings in a horizontal direction, and the second sub marker is two groups of gratings in a vertical direction. Multiple layers can be aligned in alignment, and lithography precision and device yield can be improved.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to an alignment mark and an alignment method thereof. Background technique [0002] In the manufacture of semiconductor integrated circuits, it is necessary to sequentially transfer the patterns on different masks to the substrate and each film layer of the substrate through lithography equipment to form circuits or micro devices. As the technology develops to smaller dimensions, the precision requirements for photolithography process alignment are getting higher and higher. [0003] There are various alignment methods and alignment marks in the lithography process, among which the scribe lane primary mark (SPM, Scribe lane Primary Mark) is often used for the alignment between the lithography layer and the layer, usually SPM is used in this lithography process The center is formed in the scribe lane (Scribe lane), and it is aligned with it during the photolithography...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/544H01L21/66
Inventor 舒强
Owner SEMICON MFG INT (SHANGHAI) CORP
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