Off-chip capacitor-less LDO circuit based on through silicon via array

A technology without off-chip capacitors and through-silicon vias. It can be used in the fields of adjusting electrical variables, control/regulating systems, and instruments. It can solve problems such as high static power consumption overhead, and achieve improved loop stability, noise suppression, and power supply suppression. high effect

Active Publication Date: 2017-11-28
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in order to achieve the multiplication of on-chip capacitance, the LDO circuit needs to add

Method used

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  • Off-chip capacitor-less LDO circuit based on through silicon via array
  • Off-chip capacitor-less LDO circuit based on through silicon via array
  • Off-chip capacitor-less LDO circuit based on through silicon via array

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0018] The non-external capacitor LDO circuit based on the TSV array of embodiment 1, such as Figure 1 ~ Figure 4 As shown, it includes a bandgap reference circuit, an error amplifier, a driver, an output power tube, a sampling resistor network, and a TSV capacitor. The positive input of the error amplifier is connected to the output of the sampling resistor network, and the negative input of the error amplifier is connected to the band The output terminal of the gap reference circuit is connected, the output terminal of the error amplifier is connected to the input terminal of the driver, the output terminal of the driver drives the output power transistor, and the output terminal of the output power transistor is respectively connected to one end of the sampling resistor network and one end of the TSV capacitor , the other end of the sampling resistor network is connected to the other end of the TSV capacitor and grounded, and the bandgap reference circuit, error amplifier, ...

Embodiment 2

[0025] The LDO circuit without external capacitors based on the TSV array in Embodiment 2 has the same structure as that of the LDO circuit in Embodiment 1, except that in Embodiment 2, the TSV capacitance consists of 50×50 coaxial silicon through-hole configuration. The AC characteristic curve of the LDO circuit of embodiment 2 is shown in Figure 5 . From Figure 5 From the AC characteristic curve shown, it can be seen that the DC gain of the LDO circuit is 66.13dB, the phase margin is 86.3 degrees, and the gain margin is -49.3 degrees. The entire LDO circuit can work stably. The power supply rejection ratio characteristic curve of the LDO circuit of embodiment 2 sees Figure 6 . From Figure 6 It can be seen from the power supply rejection ratio characteristic curve shown that the full frequency band power supply rejection ratio of the LDO circuit is greater than -72.5dB, which can effectively suppress the noise introduced by the input power supply.

[0026] The prese...

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PUM

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Abstract

The invention discloses an off-chip capacitor-less LDO circuit based on a through silicon via array. The off-chip capacitor-less LDO circuit comprises a band-gap reference circuit, an error amplifier, a driver, an output power transistor, a sampling resistor network and a through silicon via capacitor. A positive input terminal of the error amplifier is connected with an output terminal of the sampling resistor network. A negative input terminal of the error amplifier is connected with an output terminal of the band-gap reference circuit. An output terminal of the error amplifier is connected with an input terminal of the driver. An output terminal of the driver drives the output power transistor. An output terminal of the output power transistor is respectively connected with one terminal of the sampling resistor network and one terminal of the through silicon via capacitor. The other terminal of the sampling resistor network and the other terminal of the through silicon via capacitor are connected and grounded. The band-gap reference circuit, the error amplifier, the driver and the output power transistor are respectively connected with an external input power supply. An additional capacitance multiplier circuit or off-chip capacitor is not required for the LDO circuit, noise of the external input power supply can be effectively rejected, and the off-chip capacitor-less LDO circuit has the advantages that the off-chip capacitor-less LDO circuit is good in technology compatibility, small in area, large in capacity and high in power supply rejection ratio.

Description

technical field [0001] The invention relates to the technical field of three-dimensional integrated circuits (3D ICs), in particular to an LDO circuit without off-chip capacitance based on a through-silicon via array. Background technique [0002] With the rapid development of portable electronic products, the demand for power management chips has increased dramatically. The main purpose of power management is to improve the efficiency of power devices, thereby extending battery life and equipment usage time. As the most common product in power management chips, Low Dropout Regulator (LDO) has the advantages of simple circuit, low noise and low power consumption, and is widely used in various electronic devices. [0003] According to whether there is an off-chip capacitor, the LDO circuit can be divided into an LDO circuit with an off-chip capacitor and an LDO circuit without an off-chip capacitor. In order for the LDO system loop to work normally, the LDO circuit with off...

Claims

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Application Information

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IPC IPC(8): G05F1/56
CPCG05F1/561
Inventor 钱利波桑吉飞何锡涛励达
Owner NINGBO UNIV
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