8 results about "Impedance inverter" patented technology

The invention relates to a Doherty power amplifier with a harmonic frequency resonant circuit. A Doherty power amplifier includes a combining node that combines amplified output signals from first and second amplifiers. A reconfigurable impedance inverter circuit is coupled between a first amplifier and the combining node. The impedance inverter circuit includes an inductive element coupled between a first node and a second node, and a switching circuit coupled between the first node and the second node. A fundamental frequency tuning circuit and a harmonic frequency resonant circuit are coupled between the switching circuit and a ground reference node. When the switching circuit is configured to be in a first state, the fundamental frequency tuning circuit and the harmonic frequency resonant circuit are electrically coupled to a first node and a second node through the switching circuit. When the switching circuit is configured to be in a second state, the fundamental frequency tuning circuit and the harmonic frequency resonance circuit are electrically disconnected from the first node and the second node.

The present disclosure relates to a diplexer with an impedance inverter. The diplexer can be used to isolate a transmitter and a receiver that share a common antenna. The diplexer is balanced by using an impedance gradient that provides an impedance that causes a balun of the diplexer to cut off access to the common antenna rather than replicate the antenna impedance. Such a cut off can have lower insertion loss than a diplexer that replicates the antenna impedance only to separate differential signals and common mode signals of the receiver and transmitter.

Doherty power amplifiers with an inductor-capacitor (LC) lattice for impedance inversion are disclosed. In certain embodiments, a Doherty power amplifier includes a carrier amplifier, a peaking amplifier, and an LC lattice that serves as an impedance inverter for combining a differential carrier signal from the carrier amplifier with a differential peaking signal from the peaking amplifier. The LC lattice can include series inductors and cross capacitors connected to form a lattice, or series capacitors and cross inductors connected to form the lattice.

A Doherty power amplifier includes a combining node that combines amplified output signals from first and second amplifiers. A reconfigurable impedance inverter circuit is coupled between the first amplifier and the combining node. The impedance inverter circuit includes an inductive element coupled between a first node and a second node, and a switching circuit coupled between the first node and the second node. A fundamental frequency tuning circuit and a harmonic frequency resonance circuit are coupled between the switching circuit and a ground reference node. When the switching circuit is configured in a first state, the fundamental frequency tuning circuit and the harmonic frequency resonance circuit are electrically coupled through the switching circuit to the first and second nodes. When the switching circuit is configured in a second state, the fundamental frequency tuning circuit and the harmonic frequency resonance circuit are electrically disconnected from the first and second nodes.

Technologies are disclosed that implement impedance inversion using a combination of transmission lines and lump elements to provide a targeted transformation or inversion. These impedance inverters or transformers use a hybrid approach, combining transmission lines with lump elements, where the transmission lines provide a first fraction of a targeted overall phase shift and the lump elements provide a second fraction of the targeted overall phase shift so that the combination of the elements provides the targeted overall phase shift. The first fraction can be less than 50% and the second fraction can be greater than 50% so that the phase shift is not evenly divided between the components of the hybrid impedance inverters.

A time delay circuit includes a first port, a second port, a reference path coupled between the first and second ports, a delay path coupled between the first and second ports, and a control circuit configured to activate one of the reference path and the delay path. The reference path includes a series transistor and a first inductor connected in parallel with the series transistor. The delay path includes a first shunt transistor, a second inductor connected in parallel with the first shunt transistor, and a first impedance inverter coupled between the first port and the first shunt transistor.

The invention discloses a compact low-cost multi-chip Doherty power amplifier. The compact low-cost multi-chip Doherty power amplifier comprises a power divider, a carrier input matching network, a carrier transistor, a peak phase compensation input matching network, a peak transistor, a carrier impedance inversion output matching network and a peak output matching network. Wherein the power divider, the carrier input matching network, the carrier transistor, the peak phase compensation input matching network and the peak transistor form an amplification integrated circuit chip, and the high-mobility gallium nitride transistor can provide higher output power; the carrier impedance inversion output matching network and the peak value output matching network form a matching integrated circuit chip, and the matching integrated circuit chip preferably adopts a gallium arsenide thick gold process or a ceramic thick gold process, so that the cost can be reduced, and the function integration level can be improved. According to the invention, the reliability and consistency of the amplifier are enhanced, and a one-stop high-performance radio frequency microwave amplification solution can be provided for consumer electronics and communication equipment.

A multi-path amplifier (e.g., a Doherty amplifier) includes a first transistor (e.g., a main amplifier FET), a second transistor (e.g., a peak amplifier FET), a combining node, and a shunt inductive circuit. The first and second amplifiers and the combining node structure are formed integral with a semiconductor die, and the shunt inductive circuit is integrated with the die. Outputs of the first and second transistors are electrically coupled to the combining node structure. The shunt inductive circuit is electrically coupled between the combining node structure and a ground reference node. The shunt inductive circuit includes a shunt inductance (e.g., including one or more wire bonds and / or one or more spiral inductors) integrated with the semiconductor die. The multi-path amplifier can also include an integrated phase shifter / impedance inverter coupled between the outputs of the first and second transistors, and the integrated phase shifter / impedance inverter is configured to apply a 90 degree phase delay between intrinsic drains of the first and second transistors.