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One-time programmable memory

In the present invention, one-time programmable memory includes a diode as an access device and a capacitor as a storage device, the diode includes four terminals, wherein the first terminal is connected to a word line, the second terminal is connected to one plate of the capacitor, the third terminal is floating, and the fourth terminal is connected to a bit line, and the capacitor includes two electrodes, wherein one of the capacitor plate serves as a storage node which is connected to the second terminal of the diode, and another plate of the capacitor is connected to a plate line, and the plate line is asserted to programming voltage which is higher than the regular supply voltage of the decoders and data latches, in order to breakdown the insulator of the capacitor when programming, but the plate line is connected to the regular supply voltage when read. And during read, the diode also serves as a sense amplifier to detect whether the storage node is forward bias or not, and it sends binary data to a latch device wherein includes a current mirror and a feedback loop, which cuts off the current path after latching. And dummy columns generate replica delay signals which guarantee timing margin and reduce cycle time. In addition, the memory cells are formed in between the routing layers, which memory cells can be stacked over the transistor or another capacitor memory cell.
Owner:KIM JUHAN

One-time programmable memory

In the present invention, one-time programmable memory includes a diode as an access device and a capacitor as a storage device, the diode includes four terminals, wherein the first terminal is connected to a word line, the second terminal is connected to one plate of the capacitor, the third terminal is floating, and the fourth terminal is connected to a bit line, and the capacitor includes two electrodes, wherein one of the capacitor plate serves as a storage node which is connected to the second terminal of the diode, and another plate of the capacitor is connected to a plate line, and the plate line is asserted to programming voltage which is higher than the regular supply voltage of the decoders and data latches, in order to breakdown the insulator of the capacitor when programming, but the plate line is connected to the regular supply voltage when read. And during read, the diode also serves as a sense amplifier to detect whether the storage node is forward bias or not, and it sends binary data to a latch device wherein includes a current mirror and a feedback loop, which cuts off the current path after latching. And dummy columns generate replica delay signals which guarantee timing margin and reduce cycle time. In addition, the memory cells are formed in between the routing layers, which memory cells can be stacked over the transistor or another capacitor memory cell.
Owner:KIM JUHAN
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