2 results about "Fringing capacitance" patented technology

A field effect transistor (FET) device is provided. The FET device includes an active region and a gate. The active region includes a source at a first end thereof and a drain at a second end thereof. The gate extends across the active region and includes at least one end that extends beyond a corresponding edge of the active region by a sub-lithographic dimension.

A semiconductor device includes a substrate, a gate oxide layer formed on the substrate, a gate formed on the gate oxide layer, and a spacer formed adjacent the gate and over the substrate. The spacer includes a void filled with air to prevent leakage of charge to and from the gate, thereby reducing data loss and providing better memory retention. The reduction in charge leakage results from reduced parasitic capacitances, fringing capacitances, and overlap capacitances due to the low dielectric constant of air relative to other spacer materials. The spacer can include multiple layers such as oxide and nitride layers. In some embodiments, the semiconductor device is a multiple-time programmable (MTP) memory device.