16 results about "Fringing capacitance" patented technology

The embodiment of the invention discloses a wide-range dielectric constant standard substance and a traceable valuing method thereof. The standard substance is based on a four-stage material system of high density polyethylene (HDPE), polyvinylidene fluoride (PVDF), aluminum oxide (Al2O3) and barium titanate (BaTiO3), and wide-range coverage of a single-piece dielectric constant epsilon r of 2.3-118 is realized through volume ratio regulation and control. And an annular retaining ring electrode structure (1-3mm unplated area is reserved on the edge) is adopted, so that the edge capacitance is inhibited to be less than 0.03% of the total capacitance, and the traditional edge correction is avoided. According to the constant value method, a sodium chloride solution (0.760 mol.kg <-1 >) is taken as a first-grade standard, and a quantity value is transmitted through a parallel plate clamp constant, so that the calibration requirement of a frequency band of 100Hz-1MHz is met. The uncertainty is less than or equal to 0.6% (k = 2), and the problems of narrow mass range, complex operation and difficult traceability of the existing standard substance are solved.

A semiconductor device includes a first capacitor block including a first conductive plate, and first lower electrodes on the first conductive plate, a second capacitor block including a second conductive plate spaced apart from the first conductive plate, and second lower electrodes on the second conductive plate, a first edge capacitor block including first edge electrodes on the first conductive plate and surrounding the first capacitor block, a second edge capacitor block including a second edge electrodes on the second conductive plate and surrounding the second capacitor block and a first electrode support which supports the first lower electrodes, the second lower electrodes, the first edge electrodes, and the second edge electrodes. A first penetration pattern penetrates the first electrode support, is over the first lower electrodes and the second lower electrodes, and is not over the first edge electrodes and the second edge electrodes.

The application belongs to the technical field of power semiconductors, and particularly relates to a GaN HEMT power device with a built-in RC circuit. On the basis of ensuring a certain P-GaN layer thickness and changing GaN from depletion mode to enhancement mode by depleting two-dimensional electrons, n-doped GaN and p-doped GaN are reflected between the P-GaN layer and the metallized gate. The intrinsic GaN capacitance and the edge capacitance in the traditional structure are changed. The structure can effectively increase the gate resistance, effectively increase the edge capacitance on the gate-source side and the gate-drain side, form a built-in RC absorber, and effectively solve the problems of loss and efficiency reduction caused by the external RC circuit of GaN. Meanwhile, the GaN device itself has certain EMI resistance.

A transistor device and method of making the same are disclosed. The transistor device includes one or more air gaps in one or more sidewall spacers. The one or more air gaps may be located adjacent the gate and / or above the source or drain regions of the device. Various embodiments may include different combinations of air gaps formed in one or both sidewall spacers. Various embodiments may include air gaps formed in one or both sidewall spacers adjacent to the gate and / or above the source or drain regions of the device. The formation of the air gaps may reduce unwanted parasitic and / or fringing capacitance.

A field effect transistor (FET) device is provided. The FET device includes an active region and a gate. The active region includes a source at a first end thereof and a drain at a second end thereof. The gate extends across the active region and includes at least one end that extends beyond a corresponding edge of the active region by a sub-lithographic dimension.

Provided in the present embodiment are a bulk acoustic wave resonance device, a filter device and a radio frequency front-end device. The bulk acoustic wave resonance device comprises: a first layer comprising a cavity; a first electrode layer having at least one end located in the cavity; a piezoelectric layer, which is located on the first electrode layer to cover the cavity and comprises a first side and a second side opposite the first side, the first electrode layer being located on the first side; a second electrode layer located on the second side and on the piezoelectric layer, the portion of the second electrode layer that overlaps the first electrode layer being located above the cavity and corresponding to the cavity; and a first composite structure, which is located on the first side, comes into contact with the piezoelectric layer, and is adjacent to the first electrode layer in a horizontal direction, wherein a first end of the first composite structure close to the first electrode layer is located in the cavity, and a second end thereof opposite the first end in the horizontal direction and away from the first electrode layer is embedded into the first layer, and the first composite structure comprises a first edge extension layer and a first support layer that is located between the piezoelectric layer and the first edge extension layer. The bulk acoustic wave resonance device is used to reduce fringe capacitance, increase an electromechanical coupling coefficient, and block leaky waves, thereby increasing a Q value.

The funnel-shaped comb tooth comprises funnel-shaped comb tooth structures, comb tooth root filling blocks, a fixed polar plate and a movable polar plate, the fixed polar plate and the movable polar plate are oppositely arranged, the funnel-shaped comb tooth structures are arranged on the side faces, facing each other, of the fixed polar plate and the movable polar plate, and the comb tooth root filling blocks are arranged on the side faces, facing each other, of the fixed polar plate and the movable polar plate. The funnel-shaped comb tooth structures are arranged on the fixed polar plate and the movable polar plate at intervals, and the comb tooth root filling blocks are arranged at intervals of the funnel-shaped comb tooth structures; the wider end of the funnel-shaped comb tooth structure is respectively connected with the fixed polar plate and the movable polar plate, and the end part of the narrower end of the funnel-shaped comb tooth structure is a plane. According to the funnel-shaped comb tooth and the MEMS accelerometer, the funnel-shaped comb tooth structure with the horizontal top end is adopted, compared with a tip end of a sawtooth-shaped comb tooth, the fringe capacitance is reduced, the linearity is improved, the intervals of the funnel-shaped comb tooth structure are filled with the comb tooth root filling blocks, and the capacitance is increased.

The invention discloses a capacitance calculation method for power transmission line icing monitoring, and relates to the technical field of power transmission line on-line monitoring, and the method comprises the steps: obtaining a simulation model of an ice viewer device through building a basic model which enables a single three-electrode array to be equivalent to two circular ring capacitors connected in parallel; according to a parallel plate edge effect and an electric field theory, establishing an edge capacitance calculation model of the circular ring capacitor; combining the parallel plate capacitance calculation model and the edge capacitance calculation model to obtain a capacitance calculation model of the single circular ring capacitor; introducing the capacitance calculation model of the single circular ring capacitor and the mutual capacitance among the adjacent three-electrode arrays into the simulation model to obtain a capacitance calculation model of the cylindrical multi-electrode array; and substituting the dielectric constant into a capacitance calculation model of the cylindrical multi-electrode array to obtain a capacitance value of the cylindrical multi-electrode array, so that the capacitance value of the cylindrical multi-electrode array in the icing environment can be accurately calculated.

A transistor device and method of making the same are disclosed. The transistor device includes one or more air gaps in one or more sidewall spacers. The one or more air gaps may be located adjacent the gate and / or above the source or drain regions of the device. Various embodiments may include different combinations of air gaps formed in one or both sidewall spacers. Various embodiments may include air gaps formed in one or both sidewall spacers adjacent to the gate and / or above the source or drain regions of the device. The formation of the air gaps may reduce unwanted parasitic and / or fringing capacitance.

The application discloses a thin film dielectric constant measurement structure and a measurement method thereof. The application sets the first and second measurement units each comprising a plurality of metal strips in series and having different line widths, measures capacitance and calculates to obtain the edge capacitance in the interlayer capacitance and the parasitic capacitance, further sets the third measurement unit comprising a plurality of metal strips in parallel, measures capacitance and calculates to obtain the in-layer coupling capacitance in the parasitic capacitance; thus, the thin film dielectric constant measurement structure provided by the embodiment can measure and exclude the parasitic capacitance interference including the edge capacitance and the in-layer coupling capacitance, obtain the thin film dielectric constant of the thin film dielectric layer under the corresponding line width by obtaining the actual capacitance, and effectively improve the precision of the capacitance and dielectric constant measurement.

The invention relates to the technical field of oil detection, and discloses a capacitive abrasive particle detection sensor based on an edge enhanced coplanar electrode structure and an online oil detection system, the sensor comprises a metal shielding shell, an integrated flow channel structure, an electrode substrate, a coplanar electrode and an electrode plate groove. The two coplanar electrodes adopt the same overall contour and edge enhancement structure, the coplanar electrodes are square, continuous and periodic groove structures are respectively formed on four edges of the coplanar electrodes, and the groove structures on the edges are the same. According to the invention, electrode design of a coplanar arrangement structure is adopted, an enhanced edge structure is introduced by considering an electrode edge effect, and an edge capacitance correction term is constructed for edge electric field correction, so that the problems of non-uniform electric field and insufficient detection precision caused by the fact that a traditional coaxial capacitance sensor does not consider the electrode edge effect are solved; electric field enhancement of the central area of the flow channel and high-sensitivity monitoring of the whole watershed are achieved, the abrasive particle detection precision and the sensor space sensitivity are improved, and the detection precision of the sensor is improved.

A display panel includes a base substrate, and pixel driving circuits disposed on the base substrate. A pixel driving circuit in the pixel driving circuits includes a driving transistor and a capacitor. A gate of the driving transistor is farther from the base substrate than an active layer of the driving transistor. An active portion of the active layer includes edges that are flush with respective edges of the gate. A first electrode plate of the capacitor is coupled to the gate of the driving transistor. A second electrode plate of the capacitor is disposed on a side of the gate away from the base substrate, and is able to shield light. Orthographic projections, on the base substrate, of the edges of the active portion that are flush with respective edges of the gate are located within an orthographic projection of the second electrode plate on the base substrate.

The present disclosure relates to a frequency selective surface, FSS, unit (200, 600) comprising a dielectric material (201, 601) having a first main side (202, 602) and a second main side (203, 603). The FSS unit (200, 600) further comprises at least a first LC circuit part (240; 640) and a second LC circuit part (241; 641) formed in at least one metallization layer (204, 214; 604) comprised in a corresponding main side (202, 203; 602), where the LC circuit parts (240, 241; 640, 641) mainly run in mutually perpendicular directions (x, y). Each LC circuit part (240, 241; 640, 641) comprises a first edge capacitor part (206, 226; 208, 228; 606, 608) connected in series with a first meandered conductor part (205a, 205c; 605a, 605c) and a second meandered conductor part (205b, 205d; 605b, 605d), which meandered conductor parts (205a, 205b; 205c, 205d; 605a, 605b; 605c, 605d) form a corresponding inductor and are connected in series with a second edge capacitor part (207, 227; 209, 229; 607, 609). Each edge capacitor part (207a, 227a; 209a, 229a; 607a, 609a) is adapted to form a corresponding combined capacitor together with a corresponding further edge capacitor part (226b, 206b; 228d, 208d; 606b, 608d).

A semiconductor device includes a first capacitor block including a first conductive plate, and first lower electrodes on the first conductive plate, a second capacitor block including a second conductive plate spaced apart from the first conductive plate, and second lower electrodes on the second conductive plate, a first edge capacitor block including first edge electrodes on the first conductive plate and surrounding the first capacitor block, a second edge capacitor block including a second edge electrodes on the second conductive plate and surrounding the second capacitor block and a first electrode support which supports the first lower electrodes, the second lower electrodes, the first edge electrodes, and the second edge electrodes. A first penetration pattern penetrates the first electrode support, is over the first lower electrodes and the second lower electrodes, and is not over the first edge electrodes and the second edge electrodes.

A semiconductor device includes a substrate, a gate oxide layer formed on the substrate, a gate formed on the gate oxide layer, and a spacer formed adjacent the gate and over the substrate. The spacer includes a void filled with air to prevent leakage of charge to and from the gate, thereby reducing data loss and providing better memory retention. The reduction in charge leakage results from reduced parasitic capacitances, fringing capacitances, and overlap capacitances due to the low dielectric constant of air relative to other spacer materials. The spacer can include multiple layers such as oxide and nitride layers. In some embodiments, the semiconductor device is a multiple-time programmable (MTP) memory device.

The application discloses a kind of GaN HEMT physical base large signal model parameter extraction methods for switch, belong to semiconductor device modeling and design field, including transistor current model parameter extraction;Transistor intrinsic gate-source and gate-drain capacitance calculation;Edge capacitance model parameter extraction.The application is accurately extracted by the mode of considering the equivalent gate voltage model parameter of source-drain interaction effect under reverse bias condition, accurately characterizes the current characteristics under the condition of drain reverse bias;Using the parameter extraction method of edge capacitance bias-dependent model, the accurate characterization of deep pinch-off region nonlinear capacitance is realized, and then the precise modeling of small signal and large signal characteristics under the off state of switch device is successfully realized.