80 results about "Silicon heterojunction" patented technology

The invention provides a heterojunction quantum well and a preparation method thereof, and the method comprises the steps: providing a substrate, and forming a heterojunction quantum well at one side of the substrate through a chemical vapor deposition method; the heterojunction quantum well comprises a first barrier layer, a quantum well layer and a second barrier layer which are stacked in sequence, the first barrier layer is located between the quantum well layer and the substrate, the first barrier layer and the second barrier layer are both made of germanium-silicon, when the heterojunction quantum well is a silicon heterojunction quantum well, the quantum well layer is a silicon quantum well layer, and when the heterojunction quantum well is a silicon quantum well layer, the second barrier layer is a silicon quantum well layer. When the heterojunction quantum well is a germanium heterojunction quantum well, the quantum well layer is a germanium quantum well layer; in the process of forming the heterojunction quantum well, the precursor is decomposed in a target temperature range, and a product obtained through decomposition is deposited on one side of the substrate to obtain the heterojunction quantum well; the precursor is subjected to multi-stage reaction during decomposition, and the target temperature range is 300-550 DEG C; the interface quality of the heterojunction quantum well can be greatly improved, the surface roughness of the film layer can be reduced, and high-quality preparation of the heterojunction quantum well is realized.

The invention belongs to the technical field of silicon heterojunction solar cells, and discloses a preparation method of a distributed photovoltaic module and a preparation method of a single-sided heterojunction solar cell. According to the preparation method disclosed by the invention, the back seed layer of the copper gate heterojunction cell is reserved by removing copper through single-side etching, the back reflection of the heterojunction cell is greatly improved through the reservation of the metal seed layer, the utilization rate of sunlight long-wave band light by the cell is increased, the short-circuit current can be effectively improved by 20-50mA, and the efficiency gain of the cell is about more than 0.2%.

This invention discloses a machine learning-based method for parameter prediction and fabrication of compound silicon heterojunction solar cells, belonging to the field of silicon heterojunction solar cells. The J-V parameters of the solar cell are used as input features, and fabrication and performance parameters are used as target labels. A variational autoencoder is used to learn the latent representation of the data, and adversarial examples are generated by calculating the gradient of the input features relative to the model loss. A multilayer perceptron network incorporating a multi-head self-attention mechanism and L2 regularization is constructed, and adversarial training is performed using an enhanced training set to accurately predict the optimal UV / ozone treatment time and cell performance parameters. The intrinsic hydrogenated amorphous silicon / silicon oxide composite passivation layer is fabricated using the optimal UV / O3 treatment time. This invention, driven by machine learning, effectively captures the complex nonlinear relationships between parameters, improves the prediction accuracy of process parameters, and shortens the R&D cycle. It also effectively suppresses atomic diffusion between intrinsic hydrogenated amorphous silicon and the molybdenum oxide transport layer, improving cell performance.

The invention provides a silicon heterojunction cell, a preparation method and a photovoltaic module, and the method comprises the following steps: heating a pretreated substrate under a vacuum condition, and obtaining a heated substrate; sequentially growing an intrinsic amorphous silicon passivation layer, n-type doped hydrogenated microcrystalline silica, a transparent oxide conductive film and a metal electrode on the front surface of the heated substrate by adopting a chemical deposition method; sequentially growing an intrinsic amorphous silicon passivation layer, three p-type selective contact layers, a transparent oxide conductive film and a metal electrode on the back surface of the heated substrate by adopting a chemical deposition method; the three p-type selective contact layers comprise a p-type hydrogenated microcrystalline silicon layer, a CO2 lightly doped p-type hydrogenated microcrystalline silicon oxygen layer and a CO2 heavily doped p-type hydrogenated microcrystalline silicon oxygen layer; the three p-type selective contact layers constructed by the invention can provide excellent conductivity, transmittance and contact performance, and the filling factor of the cell is improved, so that the photoelectric conversion efficiency of the cell is improved.

The present application relates to the technical field of solar cells, in particular to a preparation of a laminated conductive film and its application in a crystalline silicon heterojunction solar cell, a transparent conductive film and a silicon film are prepared in sequence by magnetron sputtering technology to form a laminated conductive film, the preparation process is simple and efficient, and the conductive performance is significantly improved in the air environment and the heat treatment process. The laminated conductive film has good heat resistance in the air atmosphere, and after heat treatment at 100 DEG C-400 DEG C, the conductive performance is not only not attenuated but also improved, and the laminated film structure improves the stability of the transparent conductive film in acidic substances. The laminated conductive film is applied in a crystalline silicon heterojunction solar cell, the preparation process is simple, the production line has good compatibility, the service life of the heterojunction solar cell can be effectively prolonged, the reliability of the solar cell in long-term work is improved, the low packaging cost is maintained, and the application is suitable for large-scale production of high-efficiency and long-life heterojunction solar cells.

The present disclosure discloses a high-efficiency silicon heterojunction (HJT) solar cell and a manufacturing method thereof, and belongs to the technical field of solar cells. In the solar cell of the present disclosure, an N-type crystal silicon wafer is successively provided with a thin SiO2 layer, a hydrogenated amorphous carbon silicon oxide film layer, a carbon doped SiO2 layer, an amorphous silicon doped N-type layer, a TCO conductive layer, and an electrode on a front surface; and successively provided with a thin SiO2 layer, a hydrogenated amorphous carbon silicon oxide film layer, a carbon doped SiO2 layer, an amorphous silicon doped P-type layer, a TCO conductive layer, and an electrode on a rear surface. The amorphous silicon doped P-type layer includes a lightly boron doped amorphous silicon layer and a heavily boron doped amorphous silicon layer.

The invention discloses a method for improving the photoelectric property of a transparent conductive oxide film and application, and belongs to the field of optoelectronic devices. The method comprises the following steps: growing a transparent conductive oxide film (TCO), a glass substrate or a silicon substrate by using a magnetron sputtering technology (or a reaction plasma deposition technology); and growing a gradient refractive index SiNyOx / SiOx thin film on the TCO thin film by using a radio frequency magnetron sputtering technology so as to construct the composite thin film (TCO / SiNyOx / SiOx) and improve the optical transmittance and the electrical stability of the TCO thin film. According to the invention, the optical and electrical properties of the transparent conductive oxide film can be improved, the transmission of the film is enhanced, the reflection is reduced, and the transparent conductive oxide film can be applied to crystalline silicon heterojunction solar cells or other optoelectronic devices and the like.

According to the photodiode structure, the preparation method thereof and the CMOS image sensor, the perovskite / silicon heterojunction is constructed in the photodiode structure, and the spectral response range is remarkably expanded by using the high absorption coefficient of perovskite in an ultraviolet-visible region and the light absorption advantage of silicon in a near-infrared region; after photons irradiate on the silicon and the perovskite light absorption layer to excite and generate photo-induced electron-hole pairs, holes in the perovskite light absorption layer are extracted by the photo-induced hole transport layer, photo-induced electrons enter the N-well region through the electron transport layer, the photo-induced holes in the silicon diffuse and drift to the P-type substrate, and the photo-induced electrons are collected and temporarily stored in the N-well region; the compound probability of photon-generated carriers is effectively reduced, the photoelectric response speed is increased, the preparation process is simple, the method can be compatible with an existing CMOS process technology, large-area manufacturing is easy to achieve, the manufacturing cost is reduced, and the method has great significance in promoting development of a next-generation wide-spectrum and high-sensitivity image sensor.

The invention belongs to the technical field of semiconductors and micro-nano photoelectrons, and particularly discloses a silicon-Dirac semimetal heterojunction avalanche photodetector integrated with a metal nano filtering structure and a preparation method of the silicon-Dirac semimetal heterojunction avalanche photodetector, and the silicon-Dirac semimetal heterojunction avalanche photodetector sequentially comprises a metal nano structure layer, a Dirac semimetal-silicon heterojunction layer, a multiplication layer and a substrate layer from top to bottom. According to the photoelectric detector prepared by the invention, the expansion of a near-infrared band and the enhancement of the photoelectric response of a visible light band are realized through the silicon-Dirac semimetal layer heterojunction. The metal nanostructure realizes response to a target narrow-band wave band of incident light, and has the advantages of selectable wavelength, miniaturization, easy integration and the like.

The invention relates to the technical field of solar cells, and particularly discloses a low-temperature solder grid line silicon heterojunction solar cell and a preparation method thereof. According to the solar cell, an alloy film transition layer is arranged between the surface of a silicon heterojunction solar cell and a low-temperature solder grid line; the alloy film transition layer comprises the following components in percentage by mass: 95-100% of copper and / or nickel and 0-5% of tin; the alloy film transition layer grows by an ion sputtering deposition method, and the thickness of the transition layer is 20-100 nm; the low-temperature welding flux is low-melting-point alloy welding flux; the low-melting-point alloy comprises the following components in percentage by mass: 40-99% of tin, 0-40% of lead and 0-1% of copper. By applying the method, rare noble metal indium does not need to be introduced into the solder, and silver-free manufacturing of the SHJ solar cell can be achieved under the condition that the advantages of a silk-screen printing grid line preparation process are kept.

The application discloses a kind of little indium little silver silicon heterojunction solar cell, comprising: silicon substrate, intrinsic hydrogenated amorphous silicon a-Si:H (i) sequentially arranged in substrate front surface from inside to outside, phosphorus-doped nanometer silicon oxide film nc-SiO x :H (n), front transparent conductive oxide three-layer, reflection-reducing layer SiN x :H and front electrode, intrinsic hydrogenated amorphous silicon a-Si:H (i) sequentially arranged in substrate back surface from inside to outside, boron-doped nanometer silicon film nc-Si:H (p), back transparent conductive layer AZO and back electrode.The application overcomes the optical loss of ultra-thin ITO and reduces the use of indium, through the design of light-electricity cooperation, while significantly reducing the consumption of rare metal indium and noble metal silver, high conversion efficiency is maintained.

The invention provides a germanium-silicon heterojunction bipolar transistor and a manufacturing method thereof. According to the transistor, a collector region, a field region silicon oxide layer, an outer base isolation layer, an outer base region polycrystalline silicon layer and an emitter region are sequentially formed on a substrate; afterwards, a metal or metal silicide shielding layer is arranged on the first dielectric layer covering the surface of the device, and the shielding layer is located above an area between any two of the collector electrode, the base electrode and the emitter electrode and then is covered by a second dielectric layer. The shielding layer can optimize the electric field distribution between the electrodes, significantly improve the breakdown voltage between the emitter and the base, between the collector and the base and between the collector and the emitter, and enhance the power capability and reliability of the device. Meanwhile, electric field coupling between the electrodes is effectively shielded, and related parasitic capacitance is greatly reduced. The improvement of the breakdown voltage and the reduction of the parasitic capacitance act together, and the current gain cut-off frequency, the maximum oscillation frequency and other core electrical properties of the transistor are directly improved.

A structure of a germanium-silicon heterojunction bipolar transistor and a method for forming the same, wherein the method comprises: providing a substrate, the substrate comprising a base and a collector region on the base, the collector region comprising a first region and a second region on both sides of the first region; forming a main base region on the first region and an outer base region on the second region, the outer base region being on the sidewall surface and part of the top surface of the main base region; and forming an emitter region on part of the surface of the main base region, the emitter region and the outer base region being separated from each other, and the contact area of the outer base region with the main base region being increased, which is conducive to reducing the connection resistance of the outer base region, thereby improving the cutoff frequency of the device and improving the performance of the device.

The application relates to a manganese-cadmium-sulfur / crystalline silicon composite water photolysis photocathode and a preparation method and application thereof. The method is as follows: manganese-cadmium-sulfur nanoparticles with a specific component ratio are synthesized through a hydrothermal method, then a drop-coating process is adopted, and drop-coating process parameters are controlled, so that a manganese-cadmium-sulfur / silicon heterojunction photocathode is successfully constructed on crystalline silicon with a pn junction structure and a surface pyramid light-trapping microstructure. The photocathode has excellent photocatalytic activity and water photolysis efficiency, and has good catalytic stability.

The application belongs to the technical field of semiconductors, and specifically provides a low-loss reversible-conductance silicon carbide field effect power transistor device; the application adopts a polysilicon / silicon carbide heterojunction, a silicon / silicon carbide heterojunction, a nickel oxide / silicon carbide heterojunction or an integrated Schottky diode structure to improve the reverse recovery characteristic of a silicon carbide MOSFET, realize self-reversible conductance, further realize lower reverse recovery loss and higher reverse recovery performance, finally reduce the reverse recovery loss and avoid using an off-chip freewheeling diode, and reduce the application cost and the volume of a system; at the same time, a high-k insulator and / or a super-junction structure, a nickel oxide / silicon carbide heterojunction super-junction structure and a nickel oxide / insulating layer / silicon carbide super-junction structure are further introduced; these new structures can effectively reduce the specific on-resistance while increasing the breakdown voltage, thereby reducing the on-loss and greatly improving the performance of the device.

The invention discloses a germanium-silicon heterojunction bipolar transistor and a preparation method thereof, and relates to the technical field of semiconductors. According to the germanium-silicon heterojunction bipolar transistor and the preparation method thereof, the second opening (the emitter region opening) is aligned with the epitaxial collector region which is formed in the first opening and is used as the intrinsic collector region in the vertical direction, so that the epitaxial collector region is aligned with the epitaxial collector region in the vertical direction; according to the invention, minority carriers injected from a single crystal emitter region can pass through a germanium-silicon epitaxial inner base region to reach an epitaxial collector region to be efficiently collected so as to maintain normal and good basic device functions; the area of an epitaxial collector region surrounded by a first isolation silicon nitride layer (a base region-collector region isolation silicon nitride layer) is effectively reduced to the maximum extent to ensure related parasitic capacitance, especially the minimization of parasitic base region-collector region capacitance; therefore, the performance indexes of the germanium-silicon heterojunction bipolar transistor, such as radio frequency power gain, the highest oscillation frequency and the noise coefficient, can be optimized.

The invention discloses a preparation method of a crystalline silicon heterojunction solar cell, and relates to the technical field of photovoltaic cells. The preparation method of the crystalline silicon heterojunction solar cell comprises the following steps: providing a cut silicon wafer; performing laser pre-patterning processing on the front surface of the cut silicon wafer; performing texturing and etching treatment on the cut silicon wafer after laser pre-patterning to obtain a textured silicon wafer; sequentially depositing a functional laminated structure and a transparent conductive layer on the front surface and the back surface of the textured silicon wafer; and preparing the crystalline silicon heterojunction solar cell with the silver-coated copper buried gate electrode by using a silk-screen printing process. The line width of the grid line of the silver-coated copper buried gate electrode is smaller than or equal to 25 microns, and the height-width ratio of the silver-coated copper buried gate electrode is 0.6-1.5, so that the conductive sectional area of the grid line is effectively improved while the surface line width of the silver-coated copper buried gate electrode is not increased; the silver-coated copper buried gate electrode has low gate line resistance, small shading loss and high mechanical reliability at the same time, and the photoelectric conversion efficiency is further improved.

The application discloses a method for selectively growing an inner base region of a germanium-silicon heterojunction transistor, which comprises the following steps: sequentially depositing a first dielectric layer, an outer base region polysilicon layer, a second dielectric layer and a third dielectric layer on a silicon substrate, and etching to form an inner base region window; forming a fourth dielectric layer on the inner sidewall of the inner base region window; partially etching the first dielectric layer at the bottom of the inner base region window; etching to obtain an inner base region growth window; and sequentially growing a Si buffer layer, a SiGe base region layer and a Si cap layer in the inner base region growth window. In the application, the SiGe epitaxial inner base region is selectively grown in a self-aligned manner, so that a smaller inner base region area and a more stable connection effect between the inner base region and the outer base region can be realized, and the frequency characteristics and stability of the SiGe heterojunction transistor are further improved, so that the application technical field with more extensive and higher requirements is met, and the electrical performance of a chip is improved.

The invention relates to a graphene / Cu NPs / silicon heterojunction-based Schottky solar cell preparation method, which relates to the photovoltaic technical field, and comprises the following steps: 1) pre-treating a silicon wafer; 2) evaporating a copper nano film on the surface of the pretreated silicon wafer; 3) depositing a graphene film on the copper nano film; 4) carrying out annealing treatment on the heterojunction; 5) evaporating an electrode layer on the back surface of the silicon wafer; and 6) evaporating an electrode layer on the front surface of the silicon wafer. According to the preparation method of the Schottky solar cell based on the graphene / Cu NPs / silicon heterojunction, the photoelectric conversion efficiency of the Schottky solar cell is remarkably improved to 15% or above, meanwhile, the material cost is reduced to 1 / 100 of that of a traditional precious metal system, and 2-5 nano copper nanoparticles formed after annealing have triple functions in the cell at the same time, so that the photoelectric conversion efficiency of the Schottky solar cell is greatly improved. As a back electrode material, the material cooperates with a silver-aluminum electrode to provide a low-resistance conductive path, the contact resistance is lower than 0.1 ohm square centimeter, an efficient Schottky junction is formed with a silicon substrate interface to enhance light capture, and the light absorption efficiency is improved by 30%.

The invention provides an infrared silicon-based germanium waveguide structure and a preparation method thereof, and the method comprises the steps: providing a substrate, carrying out the directional growth of a germanium waveguide material in a preset growth region of the silicon substrate based on a selective area epitaxial growth technology, forming a germanium epitaxial layer, and carrying out a series of planarization shaping processing of the germanium epitaxial layer, and forming a unique inverted ridge waveguide structure germanium waveguide layer. According to the invention, the convex ridge part of the germanium waveguide layer is directly formed on the surface of the silicon substrate, and the flat plate part of the germanium waveguide layer is formed on one side, far away from the silicon substrate, of the convex ridge part, so that coupling of a transmission light field and a defect at a germanium-silicon heterogeneous interface can be effectively reduced, absorption of the defect to transmission light is inhibited, and the transmission efficiency is improved. And thus, low-loss optical signal transmission is realized in an infrared band.

The invention provides a method for preparing a perovskite / silicon heterojunction through a physical vapor deposition method and application of the perovskite / silicon heterojunction. Comprising the following steps: (a) synthesizing perovskite powder: completely dissolving cesium halide and lead halide in dimethyl sulfoxide according to a certain molar ratio, then adding an anti-solvent, separating out yellow precipitate, centrifuging the yellow precipitate, and carrying out vacuum drying to obtain the perovskite powder; (b) preparing a heterojunction composite material, namely preparing the heterojunction material by adopting a physical vapor deposition process, putting the obtained perovskite powder into a crucible, putting the crucible under a monocrystalline silicon substrate with a crystal phase of (100), vacuumizing, heating the crucible at a certain temperature to melt and evaporate the perovskite until the perovskite reaches the substrate above, and then, carrying out heat preservation on the substrate to obtain the heterojunction composite material. The substrate needs to be maintained at a certain temperature and rotating speed, and the compact and uniform silicon / perovskite heterojunction composite material can be obtained after a certain period of time. The composite material has excellent photoelectric properties, and has a wide application prospect in diode type photoelectric detectors.

The invention discloses a germanium-silicon heterojunction bipolar transistor and a manufacturing method thereof, and relates to the technical field of semiconductors, in particular to the field of process design and manufacturing of semiconductor devices and integrated circuits. According to the germanium-silicon heterojunction bipolar transistor and the manufacturing method thereof provided by the invention, the collector region, the outer base region and the emitter region of the germanium-silicon heterojunction bipolar transistor adopt metal structures instead of traditional silicon and polycrystalline silicon structures, so that the resistance of the collector region, the outer base region and the emitter region can be further reduced; therefore, the electrical properties of the germanium-silicon heterojunction bipolar transistor, such as cut-off frequency fT and maximum oscillation frequency fmax, are improved.

The invention discloses a crystalline silicon solar cell structure based on an MXene transparent electrode, and belongs to the technical field of photovoltaics. The structure is based on a crystalline silicon substrate, a passivation layer, a carrier transport layer and an MXene transparent conductive layer are sequentially arranged on at least one surface of the crystalline silicon substrate, and a metal grid line electrode is prepared on the surface of the MXene layer. The structure can be adapted to various crystalline silicon cell types such as a silicon heterojunction solar cell (SHJ) and a tunneling oxide passivation contact cell (TOPCon). The MXene transparent electrode has high conductivity, an adjustable work function and high transmittance, can realize energy level matching with different battery structures and improve the charge collection function, and meanwhile, avoids damage of a traditional magnetron sputtering process to a functional layer. The MXene transparent electrode is prepared through a solution method, so that the production cost is reduced, the photoelectric conversion efficiency of the cell is effectively improved in combination with the optimized interface design, and a novel high-performance transparent electrode solution is provided for the crystalline silicon solar cell.

The invention discloses a CdSe / ZnS quantum dot film and a preparation method and application thereof, and the preparation method comprises the following steps: mixing CdSe / ZnS quantum dots with toluene, and carrying out ultrasonic treatment to obtain a CdSe / ZnS quantum dot toluene solution; dripping the CdSe / ZnS quantum dot toluene solution on a crystalline silicon heterojunction solar cell, and drying after spin coating; and carrying out photon sintering under a protective atmosphere, and then carrying out annealing treatment to obtain the CdSe / ZnS quantum dot film. According to the invention, the CdSe / ZnS quantum dot toluene solution is spin-coated on the surface of the solar cell and photon sintering is carried out, so that densification of a quantum dot film is rapidly realized, PLQY of quantum dots is improved, resistance of a silver gate on the cell is substantially reduced, FF of the cell is improved, metal oxidation and thermal degradation of an interface passivation layer are avoided, and efficiency of the cell is improved.

The invention provides a passivation contact crystalline silicon heterojunction solar cell which can be applied to the technical field of solar cells. The passivation contact crystalline silicon heterojunction solar cell comprises a first transparent conductive layer, an N-type microcrystalline silicon oxygen layer, a first intrinsic amorphous silicon oxygen passivation layer, N-type crystalline silicon, a second intrinsic amorphous silicon oxygen passivation layer, an undoped tin oxide hole transport layer and a second transparent conductive layer which are stacked in sequence, the undoped tin oxide hole transport layer is obtained by deposition through a reaction plasma deposition method; the second transparent conductive layer includes an element doped tin oxide. The invention further provides a preparation method of the crystalline silicon heterojunction solar cell.

The application discloses a germanium-silicon heterojunction bipolar transistor and a manufacturing method thereof, relates to the technical field of semiconductors, and particularly relates to the fields of semiconductor device and integrated circuit process design and manufacturing. The germanium-silicon heterojunction bipolar transistor and the manufacturing method thereof provided by the application can achieve the purpose of exposing the outer base region part sidewall of the polysilicon so as to make necessary space for a germanium-silicon connecting base region which is synchronously grown with an inner base region of a germanium-silicon epitaxial layer in the subsequent process, and realize a recessed germanium-silicon connecting base region structure which can effectively improve the performance of the device. Moreover, the germanium-silicon heterojunction bipolar transistor provided by the application can be manufactured by using a process step which has relatively low process difficulty and complexity, and avoids the process step of using a bottom slit to "dig" the silicon nitride sidewall in the isotropic etching process which is difficult to control in the background art, so that the repeatability, uniformity, controllability and producibility of the related integrated circuit process production can be effectively improved.

The invention belongs to the technical field of materials, and particularly relates to a silicon heterojunction solar cell structure based on a phosphate electron selective transmission layer and a preparation method. According to the method, a phosphate film is prepared, and a metal compound film with phosphate radicals is introduced as an electron selective transmission layer. The mechanism that the material can be used as an electron selective transmission layer is that the phosphate film has the condition of becoming the electron selective transmission layer due to the self-doping effect of phosphorus atoms of the phosphate film. The method has the advantages of low cost, simple process and the like, and the obtained material can be used in the field of crystalline silicon cells.

The invention discloses a silicon heterojunction cell, a preparation method and application, and relates to the technical field of solar cells. The silicon heterojunction battery comprises a battery body, the battery body comprises a TCO layer and a main grid printed on the TCO layer, a self-assembly monomolecular layer is further arranged on the side, where grid lines are printed, of the TCO layer, the TCO layer and the self-assembly monomolecular layer are bonded through Si-O-M bonds and / or C-O-M bonds, M is selected from at least one of C, In and Sn, and the main grid is printed on the TCO layer. The self-assembled monomolecular layer comprises a polymer prepared by taking a self-assembled compound as a raw material, and the self-assembled compound comprises at least one of a silane compound, a spiropyrane compound and an o-nitrobenzyl ester compound. The introduction of the self-assembled monomolecular layer is beneficial to enhancing the damp-heat reliability of the silicon heterojunction battery and the assembly.

The utility model discloses a mask plate for manufacturing a grid line electrode of a crystalline silicon heterojunction battery, which is characterized in that the middle part of a first mask plate is provided with a first sinking area, the periphery of the first sinking area is respectively provided with a first sinking step, the first sinking area is provided with a plurality of grid line slits which are arranged at intervals, and the grid line slits vertically penetrate through the first mask plate; the first mask plate is used for placing a battery piece in a magnetron sputtering process or an evaporation coating process and is matched with the coating process to carry out sputtering on the surface of the battery piece to obtain the grid line slits with corresponding shapes; according to the utility model, the first mask plate is made of a high-temperature-resistant and corrosion-resistant metal material or a carbon fiber material, the first mask plate is used for placing the battery piece, and the metalized grid line electrode of the HJT battery is prepared by using a magnetron sputtering process or an evaporation coating process, so that the production cost of the HJT battery is reduced, and the photoelectric conversion efficiency of the HJT battery is improved.

The present application relates to the field of integrated photonics on chip, more particularly, to a high-efficiency on-chip acousto-optic deflector and a preparation method thereof. The acousto-optic deflector comprises a lithium niobate-silicon nitride heterostructure arranged on a silicon oxide substrate, and the lithium niobate-silicon nitride heterostructure comprises a lithium niobate thin film and a multimode coupler structure formed by silicon nitride. An interdigital transducer capable of exciting acoustic waves is arranged on the lithium niobate thin film. In the present application, the piezoelectric property of lithium niobate and the acousto-optic effect are utilized, the interdigital transducer and the multimode coupler principle in the photonic waveguide are integrated, and the Bragg diffraction is generated by the periodic structure formed by the photons and the acoustic waves, so as to finally realize deflection. The above-mentioned acousto-optic deflector reduces the size of the on-chip acousto-optic deflector, enhances the interaction between phonons and photons, and improves the efficiency. The lithium niobate and silicon nitride materials used are stable in properties, easy to process, and can be realized in large-scale integration on chip.