609 results about "Very high frequency" patented technology

An Electromagnetic Field Communications System for Wireless Networks for producing an electromagnetic field within a structure is disclosed. The electromagnetic field is produced by using common conductive elements already present within virtually all pre-existing residential commercial, industrial buildings. These conductors, which may include electrical ground shields, wiring, pipes, sprinkler conduits or structural members, are excited with a signal, and become the cavity which contains the electromagnetic field. In preferred embodiments of the invention, signals are generated using the High Frequency, Very High Frequency and lower UHF bands (3 to 30, 30 to 300 and up to 400 MHz). The invention may be used to create a local area network inside the field and within the structure. Devices that include receivers tuned to the electromagnetic field may then be connected and networked. The system may be operated without causing interference to other conventional radio devices outside the structure in the HF band.

A radar altimeter system with a closed-loop modulation for generating more accurate radar altimeter values. The present invention combines flight safety critical sensors into a common platform to permit autonomous or semi-autonomous landing, enroute navigation and complex precision approaches in all weather conditions. An Inertial Navigation System (INS) circuit board, a radar altimeter circuit board and a Global Navigation Satellite System (GNSS) circuit board are housed in a single chassis. VHF (Very High Frequency) Omni-directional Radio (VOR), Marker Beacon (MB), and VDB (VHF Data Broadcast) receiver circuit boards may also be implemented on circuit boards in the chassis.

A scheme for multi-frequency at-speed logic Built-In Self Test (BIST) is provided. This scheme allows at-speed testing of very high frequency integrated circuits controlled by a clock signal generated externally or on-chip. The scheme is also applicable to testing of circuits with multiple clock domains which can be either the same frequency or different frequency. Scanable memory elements of the digital circuit are connected to define plurality of scan chains. The loading and unloading of scan chains is separated from the at-speed testing of the logic between the respective domains and may be done at a faster or slower frequency than the at-speed testing. The BIST controller, Pseudo-Random Pattern Generator (PRPG) and Multi-Input Signature Register (MISR) work at slower frequency than the fastest clock domain. After loading of a new test pattern, a clock suppression circuit allows a scan enable signal to propagate for more that one clock cycle before multiple capture clock is applied. This feature relaxes the speed and skew constraints on scan enable signal design. Only the capture cycle is performed at the corresponding system timing. A programmable capture window makes it possible to test every intra- and inter-domain at-speed without the negative impact of clock skew between clock domains.