8 results about "Substrate doping" patented technology

Provided are a solar cell, a method for preparing a solar cell, a tandem solar cell, and a photovoltaic module. The solar cell includes a substrate, a doped conductive layer, and a dielectric layer. The substrate has a first surface, where the first surface includes electrode regions and non-electrode regions that are alternatingly arranged along a first direction. The doped conductive layer is formed over the first surface of the substrate. The doped conductive layer includes first conductive portions and at least one second conductive portion. Each respective first conductive portion of the first conductive portions is formed over a respective electrode region of the electrode regions, and each respective second conductive portion of the at least one second conductive portion is formed over a part of a non-electrode region of the non-electrode regions. The dielectric layer is between the first surface and the doped conductive layer.

A kind of silicon carbide ohmic contact electrode structure without step etching, epitaxial layer different from substrate doping type is grown on the surface layer of silicon carbide substrate piece, metal electrode array is manufactured on the surface of epitaxial layer, the manufacturing process of metal electrode does not need to rely on complex micro-nano manufacturing photoetching, etching and other processes, but uses tape with uniform edge geometry as mask to separate ohmic contact electrodes, finally, the sample is uniformly cut, and rectangular transmission line electrode without step is formed;The present application realizes the preparation of silicon carbide ohmic contact electrode with simpler structure and smaller leakage current error based on rectangular transmission line (TLM) principle, overcomes the complex process problem of traditional electrode rectangular transmission line method, reduces manufacturing cost while greatly shortens electrode preparation time, and is easy to realize.

A method for doping a semiconductor substrate includes: a preparation step for preparing conditioned water which has a pH of 2 or more and in which the concentration of a dopant element has been adjusted; an application step for applying the conditioned water to a semiconductor substrate; and a heating step for heating the semiconductor substrate to which the conditioned water has been applied. The conditioned water preparation step includes: an addition step for adding a concentration adjustment agent containing a dopant component to water to be treated and controlling the amount of the concentration adjustment agent added; and a pH adjustment step for adjusting the pH of the water to be treated before or after the addition of the concentration adjusting agent.

The present application provides a Group III element nitride substrate having excellent processability. The Group III element nitride substrate doped with a transition element has an absorption coefficient of light having a wavelength λ of 400 nm or more of 22 cm －1 The above.

A SiC substrate (10) is doped with vanadium. A high electron mobility transistor (20) is provided on the SiC substrate (10). The SiC substrate (10) includes a first substrate (1) and a second substrate (2) provided on the first substrate (1). Vanadium concentration of the first substrate (1) is 1×1018 cm−3 or more. Vanadium concentration of the second substrate (2) at an interface between the second substrate (2) and the high electron mobility transistor (20) is 1×1017 cm−3 or less.

Disclosed are a solar cell, a tandem solar cell, and a photovoltaic module. The solar cell includes a substrate, a doped semiconductor layer, a passivation layer and a plurality of electrodes. The substrate is provided with textured structures on a portion of a surface of the substrate. The doped semiconductor layer is disposed on the substrate. The solar cell further includes holes extending through the doped semiconductor layer, and corresponding to the textured structures, respectively, and a bottom of a respective hole exposes at least a portion of a corresponding textured structure. The passivation layer is formed over a surface of the doped semiconductor layer away from the substrate, fills the holes. The plurality of electrodes are arranged along a first direction, pass through the passivation layer and are in electrical contact with the doped semiconductor layer.

The invention relates to the field of semiconductor manufacturing, in particular to a novel oxide heterojunction production method, a novel transistor and a transparent device. Growing an indium gallium oxide epitaxial layer on the substrate; and growing an aluminum gallium oxide epitaxial layer on the indium gallium oxide epitaxial layer, so that two-dimensional electron gas is formed at the interface of the indium gallium oxide epitaxial layer and the aluminum gallium oxide epitaxial layer, and an indium gallium oxide / aluminum gallium oxide heterojunction is formed. The indium gallium oxide / aluminum gallium oxide heterojunction is used for replacing traditional silicon substrate doping, so that two-dimensional electron gas is prepared at the interface of the heterojunction, high carrier concentration is achieved on the premise that an ionization impurity scattering center is not introduced, the gallium oxide-based conducting layer with high carrier concentration and high mobility is prepared, and the conductivity of the gallium oxide-based conducting layer is improved. The performance of the gallium oxide device is greatly improved, and the application scene of the gallium oxide device is greatly widened.

A method for forming a power semiconductor device, the method comprising: Providing a semiconductor wafer (101) with a phosphorus doping concentration of less than 10 15 / cm 3 , which has grown through a Czochralski process and has a first page (101a); Forming an n-type substrate doping layer (105) with phosphorus as the dopant in the semiconductor wafer (101) at the first side (101a), wherein the substrate doping layer (105) has a doping concentration of at least 10 17 / cm 3 , typically of at least 10 18 / cm 3 exhibits; Forming an epitaxial layer (110) on the first side (101a) of the semiconductor wafer (101) after forming the substrate doping layer (105) Images of a dopant layer (115) in the epitaxial layer (110) during growth of the epitaxial layer (110) by diffusion of dopants from the substrate dopant layer (105) into the epitaxial layer (110); and Forming a power semiconductor device (100) with the doping layer (115) as a functional layer of the power semiconductor device (100).