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5results about How to "Increase electron concentration" patented technology

Method for reducing contact resistance of high-al component n-algan material and application

ActiveCN114792746BReduce contact resistivityIncrease the carrier concentrationManufacturing technologyOhmic contact
This invention relates to the field of semiconductor optoelectronic device technology, specifically to a method and application for reducing the contact resistance of high-Al-content n-AlGaN materials in device manufacturing processes. The method involves surface atom adsorption and annealing of the n-AlGaN layer under a protective gas atmosphere; the atoms are Si and N atoms. This method significantly increases the carrier concentration on the material surface, thereby contributing to excellent ohmic contact performance and reducing the material's contact resistivity. It solves the problem of difficult ohmic contact preparation for high-Al-content n-AlGaN materials, especially the difficulty in forming ohmic contacts after etching. The method is simple and reproducible, effectively avoiding the complexity and instability of existing processes such as acid / alkali corrosion or high-temperature annealing. It ensures large-scale mass production and has no adverse effects on subsequent device fabrication, exhibiting good process compatibility.
Owner:PEKING UNIV

Integrierte vorrichtung, halbleiterbauelement und herstellungsverfahren für die integrierte vorrichtung

InactiveAT1892577Timprove capacitor integration density of integratedincrease capacity
An integrated device, a semiconductor device, and an integrated device manufacturing method are provided, to improve capacitor integration density of the integrated device. The integrated device in embodiments of this application includes: A first dielectric layer is disposed on a first metal layer; the first metal layer, the first dielectric layer, and a gate metal layer on the first dielectric layer form a first capacitor; the gate metal layer, a second dielectric layer on the gate metal layer, and a second metal layer on the second dielectric layer form a second capacitor; and the first metal layer is connected to the second metal layer through a first conductor structure, so that the first capacitor and the second capacitor are connected in parallel.
Owner:HUAWEI TECH CO LTD

Silicon carbide-based trench MOSFET with integrated superjunction structure and its fabrication method

ActiveCN115621300BHigh cell integrationincrease electron concentrationCarbide siliconTrench mosfet
This invention discloses a silicon carbide-based trench MOSFET with an integrated superjunction structure and its fabrication method. The structure includes an n++ type silicon carbide substrate, an n-type drift layer, a p-type channel layer, a p-type shielding layer, a p++ type source region layer, and an n++ type source region layer. The n-type drift layer is disposed on the first surface of the n++ type silicon carbide substrate. A superjunction structure is integrated below the p-type channel layer and the p-type shielding layer. The superjunction structure includes a first n+ pillar region, a p+ pillar region, and a second n+ pillar region. The first n+ pillar region is located in the middle, and p+ pillar regions are provided on both sides of the first n+ pillar region. A second n+ pillar region is provided on the outer side of each of the two p+ pillar regions. A p-type channel layer is provided on the n-type drift layer on both sides of the superjunction structure and the first trench. Adjacent p++ type source region layers and n++ type source region layers are provided on the p-type channel layer. A gate electrode is provided above the p-type shielding layer. A gate oxide layer is provided between the gate electrode, the p-type shielding layer, and the sidewall of the second trench, which reduces the on-resistance and the electric field in the gate oxide layer at the bottom corner of the trench.
Owner:XIAMEN PURPLE SILICON SEMICON TECH CO LTD

Preparation method and low-temperature application of Te-doped tungsten niobium oxide / molybdenum niobium oxide heterojunction material

The invention discloses a preparation method and low-temperature application of a Te-doped tungsten niobium oxide / molybdenum niobium oxide heterojunction, and belongs to the technical field of secondary batteries. The preparation method specifically comprises the following steps: carrying out high-energy ball milling and alloying on WO3, Nb2O5 and Te2O5 to obtain amorphous Te-doped tungsten niobium oxide; the preparation method comprises the following steps: carrying out high-energy ball milling and alloying on MoO3, Nb2O5 and Te2O5 to obtain amorphous Te doped molybdenum niobium oxide; uniformly mixing and compacting the amorphous Te doped tungsten niobium oxide and the amorphous Te doped molybdenum niobium oxide, and performing discharge plasma sintering in an inert atmosphere to obtain the ceramic crystal Te doped tungsten niobium oxide / molybdenum niobium oxide heterojunction material. The Te-doped tungsten niobium oxide / molybdenum niobium oxide two-phase heterojunction material designed by the invention is relatively short in synthesis time, the synthesis period is shortened, the size of crystal grains is convenient to regulate and control, the crystallinity of the material is very good, the diffusion rate of lithium ions is greatly promoted by a heterojunction interface, the electron conductivity is improved by cooperating with Te doping, and the performance of the Te-doped tungsten niobium oxide / molybdenum niobium oxide two-phase heterojunction material is improved. The material can be used as a lithium ion negative electrode material with fast charging characteristic and good low-temperature performance.
Owner:HARBIN INST OF TECH

Backside illuminated image sensor and method of making the same

ActiveCN121398176Bincrease storage capacityincrease electron concentrationEngineeringMaterials science
This disclosure relates to a back-illuminated image sensor and its fabrication method, belonging to the field of integrated circuit technology. It includes: a plurality of mutually isolated N-type photosensitive layers located on the back side of a P-type substrate; the photosensitive layers include a first photosensitive layer, a second photosensitive layer, and a third photosensitive layer sequentially stacked along a direction away from the back side of the substrate; the first photosensitive layer includes a first photosensitive portion and a second photosensitive portion alternately distributed along a first direction parallel to the back side of the substrate; the second photosensitive layer includes a third photosensitive portion and a fourth photosensitive portion alternately distributed along the first direction; the third photosensitive portion is located directly above the first photosensitive portion and is connected to two adjacent second photosensitive portions; the third photosensitive layer includes a fifth photosensitive portion and a sixth photosensitive portion alternately distributed along the first direction; the fifth photosensitive portion is located directly above the third photosensitive portion; the third photosensitive portion is connected to two adjacent sixth photosensitive portions. This method can at least increase the electron concentration in the photosensitive area, improving the photosensitivity of the BSI image sensor.
Owner:NEXCHIP SEMICON CO LTD