12results about How to "Increase electron concentration" patented technology

This invention relates to the field of semiconductor optoelectronic device technology, specifically to a method and application for reducing the contact resistance of high-Al-content n-AlGaN materials in device manufacturing processes. The method involves surface atom adsorption and annealing of the n-AlGaN layer under a protective gas atmosphere; the atoms are Si and N atoms. This method significantly increases the carrier concentration on the material surface, thereby contributing to excellent ohmic contact performance and reducing the material's contact resistivity. It solves the problem of difficult ohmic contact preparation for high-Al-content n-AlGaN materials, especially the difficulty in forming ohmic contacts after etching. The method is simple and reproducible, effectively avoiding the complexity and instability of existing processes such as acid / alkali corrosion or high-temperature annealing. It ensures large-scale mass production and has no adverse effects on subsequent device fabrication, exhibiting good process compatibility.

An integrated device, a semiconductor device, and an integrated device manufacturing method are provided, to improve capacitor integration density of the integrated device. The integrated device in embodiments of this application includes: A first dielectric layer is disposed on a first metal layer; the first metal layer, the first dielectric layer, and a gate metal layer on the first dielectric layer form a first capacitor; the gate metal layer, a second dielectric layer on the gate metal layer, and a second metal layer on the second dielectric layer form a second capacitor; and the first metal layer is connected to the second metal layer through a first conductor structure, so that the first capacitor and the second capacitor are connected in parallel.

This invention discloses a silicon carbide-based trench MOSFET with an integrated superjunction structure and its fabrication method. The structure includes an n++ type silicon carbide substrate, an n-type drift layer, a p-type channel layer, a p-type shielding layer, a p++ type source region layer, and an n++ type source region layer. The n-type drift layer is disposed on the first surface of the n++ type silicon carbide substrate. A superjunction structure is integrated below the p-type channel layer and the p-type shielding layer. The superjunction structure includes a first n+ pillar region, a p+ pillar region, and a second n+ pillar region. The first n+ pillar region is located in the middle, and p+ pillar regions are provided on both sides of the first n+ pillar region. A second n+ pillar region is provided on the outer side of each of the two p+ pillar regions. A p-type channel layer is provided on the n-type drift layer on both sides of the superjunction structure and the first trench. Adjacent p++ type source region layers and n++ type source region layers are provided on the p-type channel layer. A gate electrode is provided above the p-type shielding layer. A gate oxide layer is provided between the gate electrode, the p-type shielding layer, and the sidewall of the second trench, which reduces the on-resistance and the electric field in the gate oxide layer at the bottom corner of the trench.

The invention discloses a preparation method and low-temperature application of a Te-doped tungsten niobium oxide / molybdenum niobium oxide heterojunction, and belongs to the technical field of secondary batteries. The preparation method specifically comprises the following steps: carrying out high-energy ball milling and alloying on WO3, Nb2O5 and Te2O5 to obtain amorphous Te-doped tungsten niobium oxide; the preparation method comprises the following steps: carrying out high-energy ball milling and alloying on MoO3, Nb2O5 and Te2O5 to obtain amorphous Te doped molybdenum niobium oxide; uniformly mixing and compacting the amorphous Te doped tungsten niobium oxide and the amorphous Te doped molybdenum niobium oxide, and performing discharge plasma sintering in an inert atmosphere to obtain the ceramic crystal Te doped tungsten niobium oxide / molybdenum niobium oxide heterojunction material. The Te-doped tungsten niobium oxide / molybdenum niobium oxide two-phase heterojunction material designed by the invention is relatively short in synthesis time, the synthesis period is shortened, the size of crystal grains is convenient to regulate and control, the crystallinity of the material is very good, the diffusion rate of lithium ions is greatly promoted by a heterojunction interface, the electron conductivity is improved by cooperating with Te doping, and the performance of the Te-doped tungsten niobium oxide / molybdenum niobium oxide two-phase heterojunction material is improved. The material can be used as a lithium ion negative electrode material with fast charging characteristic and good low-temperature performance.

The invention discloses a semiconductor composite material and a preparation method and application thereof. The semiconductor composite material comprises a semiconductor substrate, a functional layer and a first metal layer which are stacked in sequence, the functional layer comprises a doped layer; the doping layer comprises a compound AB and a doping element X doped in the compound AB; in the compound AB, A comprises Zn element, and B comprises at least one element of Se, Te or S; the doping element X comprises at least one of B, Al, Ga, In, Tl, Sc, Y, lanthanides or actinides. The functional layer prepared by the method has the characteristics of low work function and high electron concentration at the same time, can effectively induce selective collection of electrons, and can realize good contact between the semiconductor substrate and the first metal layer, so that the obtained semiconductor composite material has low contact resistivity; therefore, the energy loss generated when the current passes through the metal-semiconductor interface is effectively reduced, and the overall energy consumption of the device is reduced.

The present invention belongs to the technical field of ternary metal intermetallic electronic compound materials, and discloses an A2BC2 type ternary metal intermetallic electronic compound material and a preparation method and application thereof, wherein the preparation method comprises: mixing components A and C in equal atomic ratios, and then smelting to form alloy AC; crushing the alloy AC, and then mixing it with component B in an atomic ratio of 1.8 to 2.2 to obtain a mixed powder; and annealing the mixed powder to obtain the A2BC2 type ternary metal intermetallic electronic compound material. The preparation method of the present invention is simple, has a low reaction temperature, a short preparation cycle, a low preparation cost, and obtains a material with better purity and crystallinity, and has extremely strong expansibility.

The present application relates to a method for preparing a back-illuminated image sensor and the back-illuminated image sensor, comprising: providing a substrate, the substrate comprising a substrate, a plurality of first isolation structures arranged at intervals on a first surface of the substrate, and a plurality of second isolation structures located in the substrate and arranged corresponding to the first isolation structures; etching the substrate based on the first isolation structures to form a plurality of grooves in the substrate between the first isolation structures; forming an isolation layer at least on the inner sidewalls and the bottom surface of the grooves; forming a photosensitive stack on the isolation layer; wherein the isolation layer surrounds the surface of the photosensitive stack in contact with the substrate, and the plane where the top surface of the photosensitive stack is located is located between the plane where the first surface of the substrate is located and the plane where the top surface of the first isolation structure is located, thereby expanding the space of the photosensitive area formed by the photosensitive stack, increasing the electron concentration of the photosensitive area, and improving the photosensitivity of the BSI image sensor.

The invention provides a semiconductor device and a preparation method thereof, a chip and electronic equipment, relates to the technical field of semiconductors, and aims to improve the performance of the semiconductor device and prolong the service life of the semiconductor device, the semiconductor device comprises a substrate, a barrier layer, a grid electrode, a source electrode, a drain electrode and at least two first polarization enhancement parts, the barrier layer is arranged on one side of the substrate, the grid electrode is arranged on the side, away from the substrate, of the barrier layer, the source electrode and the drain electrode are arranged on the two opposite sides of the grid electrode in the first direction, the first direction is parallel to the substrate, and the at least two first polarization enhancement parts are arranged between the grid electrode and the drain electrode and arranged on the side, away from the substrate, of the barrier layer. The at least two first polarization enhancement parts are arranged at intervals along the first direction. The semiconductor device is applied to a chip.

The utility model provides a composite trench gate silicon carbide VDMOS capable of improving gate reliability, which is characterized in that the lower side surface of a drift layer is connected to the upper side surface of a silicon carbide substrate, a well region is arranged on the drift layer, a p-type source region and an N-type source region are arranged in the well region, and the side surface of the P-type source region is connected with the side surface of the N-type source region; a groove is formed in the drift layer; the high-K gate dielectric layer is arranged in the groove, and the groove is formed in the high-K gate dielectric layer; the first gate dielectric layer is arranged in the groove, the first gate dielectric layer is located above the high-K gate dielectric layer, a through hole is formed in the first gate dielectric layer, and the through hole is connected with the groove; the gate metal layer is arranged in the through hole and the groove; the source metal layer is connected to the N-type source region and the P-type source region; the drain electrode metal layer is connected to the lower side face of the silicon carbide substrate, electric field concentration at the corner of the bottom of the grid electrode has higher tolerance, and therefore the reliability of the grid electrode is improved.

This disclosure relates to a back-illuminated image sensor and its fabrication method, belonging to the field of integrated circuit technology. It includes: a plurality of mutually isolated N-type photosensitive layers located on the back side of a P-type substrate; the photosensitive layers include a first photosensitive layer, a second photosensitive layer, and a third photosensitive layer sequentially stacked along a direction away from the back side of the substrate; the first photosensitive layer includes a first photosensitive portion and a second photosensitive portion alternately distributed along a first direction parallel to the back side of the substrate; the second photosensitive layer includes a third photosensitive portion and a fourth photosensitive portion alternately distributed along the first direction; the third photosensitive portion is located directly above the first photosensitive portion and is connected to two adjacent second photosensitive portions; the third photosensitive layer includes a fifth photosensitive portion and a sixth photosensitive portion alternately distributed along the first direction; the fifth photosensitive portion is located directly above the third photosensitive portion; the third photosensitive portion is connected to two adjacent sixth photosensitive portions. This method can at least increase the electron concentration in the photosensitive area, improving the photosensitivity of the BSI image sensor.

The invention discloses an Mg3Sb2-based semiconductor material for energy conversion and a preparation method thereof, and belongs to the technical field of energy conversion, and the molecular formula of the Mg3Sb2-based semiconductor material is Mg < 3.2 > Bi < 1.3 > Sb < 0.7 >. Mg < 3.2 > Bi < 1.3 > Sb < 0.7 > can generate n-p conduction transformation; when the K is less than 500 K, Mg < 3.2 > Bi < 1.3 > Sb < 0.7 > is an n-type semiconductor; when the voltage is greater than 500 K, Mg < 3.2 > Bi < 1.3 > Sb < 0.7 > is a p-type semiconductor. The preparation method comprises the following steps: uniformly mixing magnesium powder, bismuth powder and antimony powder according to a molar ratio of 3.2: 1.3: 0.7, sealing in a pure argon environment, and carrying out alloying, cold pressing and sintering to obtain the Mg3.2 Bi1. 3Sb0.7. When Bi is doped into the Sb position, the Mg vacancy concentration in the material can be effectively reduced, and the electron concentration can be improved at the same time. The doping not only enables the energy band gap of the material to be narrowed and converted into a narrow-band-gap semiconductor, but also improves the carrier concentration of the material. Under the combined action of the two factors, the electron concentration in the material is remarkably enhanced, and then conversion from an n-type conduction type to a p-type conduction type can be achieved. Therefore, the material has huge application potential in the technical field of energy conversion.

The invention provides a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a semiconductor substrate, an epitaxial layer is formed on the surface of the semiconductor substrate, and a contact doping region is formed in the epitaxial layer; the shielding doped regions are located in the epitaxial layer on the two sides of the contact doped region, and the doping type of the shielding doped regions is opposite to that of the contact doped region; the well region is located in the epitaxial layer at the bottom of the contact doped region, the doping type of the well region is opposite to that of the contact doped region, and the depth of the shielding doped region is larger than that of the well region and larger than that of the contact doped region; the trench gate structures are located on the two sides of the shielding doped region and penetrate through part of the shielding doped region to be connected with the well region and the contact doped region, and the depth of the trench gate structures is larger than that of the well region and smaller than that of the shielding doped region. The MOSFET unit structure can solve the problems that an existing MOSFET unit structure is not high in reliability and low in integration level.