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Memory and manufacturing method thereof

一种存储器、氧化物的技术,应用在半导体/固态器件制造、电固体器件、半导体器件等方向,能够解决电子浓度降低、影响数据读取正确性、位错误等问题

Inactive Publication Date: 2008-03-05
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, since there is a lot of background radiation in the external environment where the dual-bit nitride ROM 100 is located, the electron concentration in the first storage node 133 and the second storage node 135 of the memory cell 130a is likely to decrease.
This further leads to bit errors stored in the storage unit 130a, which affects the correctness of the overall data read.

Method used

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Examples

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no. 1 example

[0038] Please refer to FIG. 2A and FIG. 2B at the same time. FIG. 2A shows a partial top view of the memory according to the first embodiment of the present invention, and FIG. 2B shows a cross-section of the memory along the section line 2B-2B' of FIG. 2A picture. 2A-2B, the memory 200 includes a substrate 210, a plurality of bit lines (bitlines) 220, a plurality of word lines (word lines) 230, a plurality of oxide / nitride / oxide (oxide-nitride-oxide, ONO) stack structure 240, a plurality of spacer layers 250, a plurality of storage units 215 (shown in larger dotted line ranges in FIG. 2A and FIG. 2B ), a plurality of first storage nodes (storagenode) 217a, a plurality of first Binary storage section 217b. The bit lines 220 are disposed parallel to each other in the substrate 210 and located near the surface of the substrate 210 . The word lines 230 are arranged parallel to each other on the substrate 210 , and the word lines 230 and the bit lines 220 cross each other, but t...

no. 2 example

[0048] Please refer to FIG. 4A and FIG. 4B at the same time. FIG. 4A shows a partial top view of the memory according to the second embodiment of the present invention, and FIG. 4B shows a cross-section of the memory along the section line 4B-4B' of FIG. 4A picture. In FIGS. 4A-4B, the memory 300 includes a substrate 310, a plurality of bit lines 320, a plurality of word lines 330, an oxide / nitride / oxide (oxide-nitride-oxide, ONO) layer 340, a plurality of memory The unit 315 (as shown by the larger dotted line in FIG. 4A and FIG. 4B ), a plurality of first bit storage sections 317a, and a plurality of second bit storage sections 317b. The bit lines 320 are disposed parallel to each other in the substrate 310 and located near the surface of the substrate 310 . The word lines 330 are arranged parallel to each other on the substrate 310 , and the word lines 330 and the bit lines 320 cross each other, but the word lines 330 and the bit lines 320 are not perpendicular to each oth...

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Abstract

A memory is provided. The memory includes a substrate, a number of parallel bit lines, a number of parallel word lines and at least a oxide-nitride-oxide (ONO) structure. The bit lines are disposed in the substrate. The word lines are disposed on the substrate. The word lines are crossed with but not perpendicular to the bit lines. The ONO structure is disposed between the word lines and the substrate.

Description

technical field [0001] The invention relates to a memory and a manufacturing method thereof, in particular to a memory in which word lines and bit lines are not vertically interlaced and a manufacturing method thereof. Background technique [0002] Please refer to FIG. 1A and FIG. 1B. FIG. 1A shows a partial top view of a conventional double-bit nitride read-only memory, and FIG. A cross-sectional view of the read memory. In FIGS. 1A-1B, a dual bit nitride read only memory (NROM) 100 includes a silicon substrate 105, a plurality of buried bit lines 110, a plurality of word lines 120, a plurality of oxide / Nitride / oxide (oxide-nitride-oxide, ONO) stack structure 130b, multiple barrier diffusion oxide (barrier diffusion oxide) layers 140, multiple memory cells (memory cell) 130a (as shown in FIG. 1A and FIG. 1B shown in the larger dotted line range), a plurality of first storage nodes (storage node) 133 and a plurality of second storage nodes 135 (shown in the smaller dotted...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/115H01L23/522H01L21/8247H01L21/768
CPCH01L27/115H01L27/0207H01L27/11568H10B69/00H10B43/30H10B43/10
Inventor 刘建宏黄守伟陈盈佐林佑聪
Owner MACRONIX INT CO LTD
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