Grooved Field Effect Positive Feedback Transistor Based on Semiconductor Substrate and Fabrication Method

Abstract

The invention discloses a groove type field effect positive feedback transistor based on a semiconductor substrate and a preparation method thereof. The positive feedback transistor uses a groove type gate oxide layer structure to improve the defects of the planar gate oxide layer positive feedback transistor. By introducing key The doping of the channel region and the inverse substrate doping and low drain doping region of the channel region form the special energy band structure required by the positive feedback mechanism, thereby achieving electrical properties similar to ordinary positive feedback transistors In addition, the positive feedback transistor has a symmetrical physical structure similar to that of a MOSFET, and can be formed on the channel region by a self-aligned ion implantation process similar to a MOSFET under the masking effect of the positive gate and the gate spacer Low drain doping region and cathode region / anode region doping; the positive feedback transistor preparation process of the present invention is compatible with traditional CMOS, increases gate oxide layer capacitance, increases charge retention time, prolongs data storage time, and improves the Device performance as memory.

Description

technical field

[0001] The invention relates to the technical field of semiconductor devices, in particular to a groove-type field-effect positive-feedback transistor based on a semiconductor substrate and a preparation method thereof. Background technique

[0002] For decades, the traditional one-transistor-capacitor dynamic random access memory (1T-1C DRAM) has shown good reliability and high integration (references: Song KW, Kim y, Kim H, Chung HW, et al. A 31ns random cycle VCat-based 4F2 DRAM with enhanced cell efficiency. Proc Symp vls Circuits 2009:132-3). For example, recently proposed popular dynamic memory devices, including capacitor-based IT-IC dynamic random access memory (DRAM) (reference: C.J.Radens, S.Kudelka, L.Nesbit, et al. "Anorthogonal 6F trench sidewall vertical device cell for 4 Gb / 16 Gb DRAM," inIEDM Tech.Dig., 2000, pp.349–352.), conventional 6-T SRAM (reference: L.Chang, D.M.Fried, J.Hergenrother , et al. "Stable SRAM cell design for the 32nmnode ...

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