54results about How to "Reduce junction depth" patented technology

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping, “wrapped” gates, epitaxially grown conductive regions, epitaxially grown high mobility semiconductor materials (e.g. silicon-germanium, germanium, gallium arsenide, etc.), high-permittivity ridge isolation material, and narrowed base regions can be used in conjunction with the segmented channel regions to further enhance device performance.

An MOS transistor comprises low doped source/drain extended regions in a semiconductor substrate and on two sides of a grid structure, sidewalls located on the semiconductor substrate on two sides of the grid structure, heavily doped source/drain regions located in the semiconductor and on two sides of the grid structure, and pocket regions and F-ion doped regions respectively located in the semiconductor substrate and on two sides of the grid structure, wherein the F-ion doped regions are located around the pocket regions. The invention further provides a method of forming the MOS transistors. By forming the F-ion doped regions around the pocket regions of the MOS transistor, transient enhanced diffusion effect of ions from the pocket regions into the semiconductor substrate can be prevented, thereby reducing junction depth, decreasing junction current leakage, and improving the performance of the MOS transistor.

The invention discloses a laterally diffused metal oxide semiconductor (LDMOS) device; the LDMOS device comprises a source region, a gate region, a drain region, a body region, and a drifting region with doped type opposite to the body region; the body region is arranged on a substrate region, and the drifting region is arranged between the drain region and the body region. The LDMOS device also comprises an insulated dielectric layer, and the insulated dielectric layer is positioned on the drifting region and below the gate region. By using the structure of the LDMOS device provided by the invention, the puncture voltage of the device can be enhanced, so that the on-resistance is lowered and the power consumption of the device is reduced; and in the adjusting and fabricating process, junction depth for adjusting the insulated dielectric layer and the drifting region has smaller effect on the other devices.

A method of forming an integrated circuit device includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a pre-amorphized implantation (PAI) by implanting a first element selected from a group consisting essentially of indium and antimony to a top portion of the semiconductor substrate adjacent to the gate structure. The method further includes, after the step of performing the PAI, implanting a second element different from the first element into the top portion of the semiconductor substrate. The second element includes a p-type element when the first element includes indium, and includes an n-type element when the first element includes antimony.

A method of manufacturing a semiconductor device including a plurality of MIS transistors formed on a semiconductor substrate, includes forming a plurality of gate electrodes associated with the MIS transistors on the semiconductor substrate, with a plurality of gate insulating films interposed between the gate electrodes and the semiconductor substrate, respectively, and successively forming a plurality of impurity diffusion regions for LDD regions in the semiconductor substrate, at decreasing junction depths, respectively, by using lithography and ion implantation, such that each of the impurity diffusion regions being provided on both sides of a respective one of the gate electrodes.

The invention discloses a process for manufacturing an emitter of a solar cell, which comprises the following steps: step A, manufacturing a PN junction on the surface of a matrix silicon wafer (1) by a diffusion process to form a surface impurity distribution layer (2); step B, oxidizing the surface impurity distribution layer (2) obtained in step A to quickly grow an oxidation layer (3) distributed uniformly on the surface of the surface impurity distribution layer (2); and step C, removing the oxidation layer (3) in step B. The process avoids the phenomenon that the ordinary diffusion process cannot avoid generating a 'dead layer', further reduces the surface concentration, improves the minority carrier lifetime and the conversion efficiency of the cell, and reduces the production cost of the solar cell.

The invention relates to a method of forming an ultra-shallow junction. The invention comprises the following steps: ions are infused into a semiconductor substrate; the pre-annealing operation is carried on to the semiconductor substrate, to heat up the semiconductor substrate from the room temperature to the intermediate temperature value; oxygen is filled, the annealing operation is carried on to the semiconductor substrate, to heat up the semiconductor substrate from the intermediate temperature value to the annealing temperature peak value; the cooling operation is carried on to the semiconductor substrate, to cool the semiconductor substrate from the annealing temperature peak value to the room temperature. A peak value annealing method is adopted in the forming process of the ultra-shallow junction, doping material activation and crystal lattice damage reconstruction can be completed simultaneously in one thermal treatment process; the oxygen is filled in the peak value annealing process, and the doping ionic diffusion is reduced.

In a method of manufacturing a NOR flash memory structure, a highly-doped ion implantation process is performed to form a highly-doped drain region to overlap with a lightly-doped drain region. Therefore, the flash memory structure can have a reduced drain junction depth to improve the short channel effect while protecting the lightly-doped drain region from being punched through during an etching process for forming a contact hole.

The invention discloses a boron diffusion method for an N-type solar cell. The boron diffusion method comprises the following steps: (1) carrying out high-temperature boron source diffusion on an N-type silicon wafer after texturing so as to obtain a P+ emitting electrode; (2) carrying out a reaction for 40 to 60 s at room temperature in a hydrofluoric acid solution to remove borosilicate glass onthe surface of the N-type silicon wafer; (3) washing the N-type silicon wafer with pure water after the borosilicate glass is removed to remove the hydrofluoric acid solution remaining on the surface; (4) putting the N-type silicon wafer after being cleaned with pure water into an NaOH solution for carrying out a reaction for 2 to 5 min so that the square resistance of the N-type silicon wafer isimproved by 8 to 20 ohm/sq; (5) putting the N-type silicon wafer after the square resistance is improved into a hydrofluoric acid and hydrochloric acid mixed solution for washing for 1 to 2 min to remove metal ions and a back oxidation layer; and (6) washing with pure water and drying. According to the method, the square resistance on the surface of the silicon wafer after boron expansion can beuniformly improved, the condition that the concentration of the surface after the boron diffusion of the N-type cell is effectively solved, and the junction depth is improved.

The invention relates to a trench triode and a manufacturing method thereof. The trench triode comprises an N-type substrate, an N-type epitaxial layer which is formed on the N-type substrate, a P-type base region which is formed on the surface of the N-type epitaxial layer, multiple trenches which penetrate through the P-type base region and extend to the N-type epitaxial layer, a P-type high doped region which is formed on the side wall of multiple trenches, P-type polycrystalline silicon which is arranged in multiple trenches, an N-type region which is formed on the surface of the P-type base region, a TEOS oxide layer which is formed on the P-type polycrystalline silicon and the -type high doped region, emitter polysilicon which is formed on the N-type region, a contact hole which penetrates through the TEOS oxide layer and is corresponding to the P-type polycrystalline silicon, front metal and back metal. The front metal comprises an emitter which is formed on the emitter polysilicon and a base electrode which is formed on the TEOS oxide layer and connected with the P-type polycrystalline silicon through the contact hole. The back metal is formed on the surface, which is awayfrom the N-type epitaxial layer, of the N-type substrate to act as the collecting electrode.

The invention belongs to the technical field of photovoltaics, and particularly relates to a preparation method of a PERC battery. The method is mainly used for improving the efficiency of the PERC battery. The method comprises a diffusion step, an etching step and a back film step which are carried out in sequence, an etching solution is adopted in the etching step, and chemical components of the etching solution comprise HNO3, HF, H2SO4 and H2O; and in the back film step, SiH4 and NH3 are adopted to carry out film coating deposition on the back surface of the silicon wafer, and the film coating deposition times is twice. Compared with the prior art, the method increases the refractive index of the silicon wafer substrate, increases the light absorption rate of the PERC cell, and increases the efficiency of the PERC cell.