Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate; a gate structure disposed on the surface of the substrate; a lightly doped region arranged in the substrate on the two sides of the gate structure and extending to be below the gate structure; an L-shaped groove and a stress layer in the L-shaped groove. The L-shaped groove is arranged in the substrate on the two sides of the gate structure. One part of the stress layer is arranged below the lightly doped region. The stress layer below the lightly doped region is of a cuboid structure. In this way, the formation of a tip structure between the stress layer and the substrate is avoided, so that the junction leakage current caused by the tip structure is avoided. Meanwhile, below a conductive channel, the stress layer of the cuboid structure is away from the conductive channel compared with a sigma-type stress layer. Therefore, the stress below the conductive channel is reduced, and the junction leakage current is further reduced.

Description

technical field [0001] The present application relates to the technical field of semiconductor integrated circuits, and in particular, to a semiconductor device and a manufacturing method thereof. Background technique [0002] As the integration of transistors in semiconductor devices becomes higher and higher, the feature size of transistors becomes smaller and smaller, and the mobility of carriers in transistors gradually decreases. This decrease in carrier mobility will not only reduce the switching speed of the transistor, but also reduce the driving current of the transistor, which ultimately leads to a decrease in the device performance of the transistor. In the prior art, technicians use stress technology, that is, by introducing local unidirectional tensile or compressive stress to the conduction channel of the transistor, so as to increase the mobility of carriers in the conduction channel of the transistor. For example, a SiGe layer is usually embedded in a PMOS d...

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Problems solved by technology

[0004] In the above-mentioned semiconductor device, since the stress layer 40' under the gate structure 20' has a pointed structure, the electric field strength near it is relatively high, thus easily generating junction leakage current between the stress layer 40' and the substrate 10'

At the same time, the lightly doped region 30' close to the conductive channel is replaced by a part of the stress layer 40', so that the stress under the conductive channel is greater, which in turn makes the junction leakage current more likely to occur

For the above problems, there is currently no effective solution

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