Semiconductor device and method of manufacturing the same

Abstract

In the semiconductor device according to the present invention, a P type diffusion layer and an N type diffusion layer as a drain lead region are formed on an N type diffusion layer as a drain region. The P type diffusion layer is disposed between a source region and the drain region of the MOS transistor. When a positive ESD surge is applied to a drain electrode, causing an on-current of a parasite transistor to flow, this structure allows the on-current of the parasite transistor to take a path flowing through a deep portion of an epitaxial layer. Thus, the heat breakdown of the MOS transistor is prevented.

Description

technical field [0001] The present invention relates to a semiconductor device that prevents destruction due to overvoltage such as Electrostatic Discharge (hereinafter referred to as ESD), and a manufacturing method thereof. Background technique [0002] As an example of a conventional semiconductor device, the following structure of a MOS (Metal Oxide Semiconductor) transistor 31 is known. [0003] Such as Figure 8 As shown, an N-type epitaxial layer 33 is formed on a P-type semiconductor substrate 32 . P-type diffusion layers 34 and 35 serving as back gate regions are formed on the epitaxial layer 33 . An N-type diffusion layer 36 serving as a source region is formed on the P-type diffusion layer 34 . Further, N-type diffusion layers 37 and 38 are formed in the epitaxial layer 33 as drain regions. A gate oxide film 39 , a gate electrode 40 , and an insulating film 41 are formed on the epitaxial layer 33 (for example, refer to Patent Document 1). [0004] Patent Docum...

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Problems solved by technology

Furthermore, since the gate oxide film 39 and the insulating film 41 etc. which are inferior in thermal conductivity to silicon are arranged on the upper surface of the epitaxial layer 33, the surface side of the epitaxial layer 33 becomes a region inferior in heat dissipation.

As a result, in the region indicated by the arrow 43, the surface side of the epitaxial layer 33 is thermally damaged due to the heat generated by the conduction current I2 of the parasitic Tr2.

For example, when an electrostatic destruction test is performed with respect to a structure in which the gate length (W) of the MOS transistor 31 is 1000 μm, the above-mentioned thermal destruction occurs below 1 A with respect to the conduction current I2 (destruction current) of the parasitic Tr2. The machine model (MM) has an ESD tolerance of 200V or less, and the human body model (HBM) has an ESD tolerance of 1000V or less, and it is not a structure that can achieve the desired ESD tolerance

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