Semiconductor device with buffer layer and manufacturing method thereof

Abstract

The invention discloses a semiconductor device having a buffer layer and a manufacturing method thereof. The semiconductor device comprises a front surface structure arranged on the front surface of the semiconductor device and a back surface structure arranged on the back surface of the semiconductor device. The back surface structure comprises a P<+> collector region and the N-type buffer layer arranged on the P<+> collector region. The P<+> collector region and the N-type buffer layer each adopt a thin film structure which is formed directly on the back surface of the semiconductor device by utilizing the low-temperature PECVD technology. The P<+> collector region and the N-type buffer layer further adopt the deposited thin film structure formed through the low temperature PECVD technology. The thin film is one or more of amorphous silicon, microcrystalline silicon, carbon-doped amorphous silicon or silicon germanium. According to the semiconductor device having the buffer layer and the manufacturing method thereof, cost of the semiconductor device and thermal budget of the silicon wafer back surface technology can be reduced effectively on the basis of not using an ion implantation device and an annealing process, and injection and extraction rate of carriers on the back surface of a silicon wafer can be adjusted according to the difference of the types of thin-film materials.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a semiconductor device with a buffer layer structure and a manufacturing method thereof. Background technique [0002] With the rapid development of power electronics and semiconductor technology, various power electronics applications require the use of specialized and professional semiconductor switching devices to achieve a balance between cost and performance. as attached figure 1 Shown is a schematic structural diagram of a field stop type IGBT device in the prior art. The field stop type IGBT device includes a P+ collector region 1, an N-substrate 3, a P-type base region 4, an N+ emitter region 5, a collector electrode 7, and an emitter electrode 8 and grid 9. Compared with traditional non-punch-through (NPT) IGBT devices, field stop IGBT further reduces saturation voltage drop and switching loss, which makes field stop IGBT devices very suitable for various soft swit...

AI Technical Summary

Problems solved by technology

However, for field-stop IGBT devices, an N-type buffer layer is also required on the back side. If only P-type amorphous silicon is formed on the back side of DMOS, and the N-type buffer layer adopts traditional technology, it is difficult to avoid high-temperature annealing process, and it is impossible to reduce the thermal budget. Effect

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