191results about How to "Lower thermal budget" patented technology

A method for depositing an amorphous carbon layer on a substrate includes the steps of positioning a substrate in a chamber, introducing a hydrocarbon source into the processing chamber, introducing a heavy noble gas into the processing chamber, and generating a plasma in the processing chamber. The heavy noble gas is selected from the group consisting of argon, krypton, xenon, and combinations thereof and the molar flow rate of the noble gas is greater than the molar flow rate of the hydrocarbon source. A post-deposition termination step may be included, wherein the flow of the hydrocarbon source and the noble gas is stopped and a plasma is maintained in the chamber for a period of time to remove particles therefrom.

The invention relates to a shallow groove isolation formation method. The method comprises the following steps: a semiconductor substrate with a groove is provided; pad oxide layers are formed on the bottom part and the side wall of the groove, and in situ annealing is performed; insulation substance is filled into the groove. The shallow groove isolation formation method of the invention can reduce the transmission frequency of the substrate, reduce the pollution, ensures the process to be simplified, and reduces the cost.

The invention relates to the field of solar cell production method, especially to a method for realizing a laminated passivation film on the back surface of a solar cell. A film is deposited on the backlight surface of a processed solar cell silicon chip according to chemical vapor deposition technology, the mixed gas of SiH4 and N2O is adopted as the gas at the beginning of the deposition, NH3 is gradually added in the process of deposition so that the component of the film is changed from silicon dioxide on the surface of the silicon chip to nitrogen oxide of silicon in the outward direction and then to silicon nitride in the outward direction, and the thickness of the film ranges from 50nm to 300nm. The method has the characteristics of fast deposition speed, high output, being capable of achieving the deposition of a plurality of films at a time, and high tightness of the deposited film. High temperature process is not needed in the technology, the heat budget required is less, and high temperature influence resulted from thermal oxidization is avoided, in addition, such a graded laminated film can effectively reduce interface state caused by the combination of different films, improve thermal stability compared with silicon nitride only, and lessen film stress.

A method for forming a side wall layer on a grid electrode comprises the following steps: a semi-conductor substrate provided with the grid electrode is provided; a first silica layer is formed on the surfaces of the semi-conductor substrate and the grid electrode; with hexa-chloro silane as a precursor, a first silicon nitride layer is formed on top of the first silica layer; and parts of the first silica layer and the first silicon nitride layer are removed in a selective manner so as to preserve the first silica layer and the first silicon nitride layer already formed on the side wall of the grid electrode. The invention further provides a method for manufacturing a semiconductor device. The invention can solve the problem that the bottom part of the side wall layer on the grid electrode is susceptible to depression.

The invention belongs to the technical field of semiconductor devices, and particularly relates to a flexible resistive random access memory based on oxidized graphene and a preparation method thereof. The flexible resistive random access memory comprises a transparent flexible substrate and a three-layer structure device unit on the substrate, the bottom layer of the device unit is a flexible transparent electrode, the top layer electrode can be metal or other electrodes, and the middle functional layer is an oxidized graphene thin film. As the experiment proves, the oxidized graphene has the good resistance change characteristics, rotating coating can be carried out at the indoor temperature to form the functional layer of the resistive random access memory, the high-temperature process required for growing other materials of the functional layer is avoided, and the obtained flexible resistive random access memory can be applied to flexible electronic devices.

The invention discloses a silicon wafer phosphorus diffusion gettering technology for manufacture of a solar cell, which comprises the following steps of: coating a phosphorus source on the surface of a silicon wafer; heating the silicon wafer to 800-1,100 DEG C at the rate of 50-200 DEG C/s in the presence of a protective gas atmosphere; preserving the temperature for 1-10 minutes; then cooling to 500-800 DEG C and preserving the temperature for 1-10 minutes; and cooling and then removing a phosphorosilicate glass layer. The invention has short process time, low cost and good gettering effect.

A surrounding gate field-effect transistor combined with a vertical channel (4) and a junction-free structure comprises a surrounding semiconductor channel in the vertical direction, a surrounding gate electrode (6), a surrounding gate dielectric layer (5), a source region (2), a drain region (3) and a semiconductor substrate (1), wherein the source region (2) is located at the bottom of the vertical channel (4) and connected with the substrate (1), the drain region (3) is located at the top of the vertical channel (4), and the gate dielectric layer (5) and the gate electrode (6) surround the vertical channel (4) circularly. The impurities of the same type and concentration are doped into the source region (2), the drain region (3) and the vertical channel (4). The same impurities are doped into source and drain channels of the transistor, so that heat budget is greatly reduced, the impurity diffusion and abrupt junction forming problems are eliminated, process requirements are simplified, integration machining photo-etching ultimate limit is broken through by utilizing the vertical channel and a surrounding gate structure, and the integration degree is improved.

The invention discloses an LDMOS device and a manufacture method thereof. The manufacture method of the LDMOS device comprises the steps of fabricating a gate region of the LDMOS device on a semiconductor substrate, employing a mask to inject a first doping matter into the semiconductor substrate obliquely at a certain angle and employing the same masking to inject the first doping matter into the semiconductor substrate vertically, wherein the region formed by inclined injection and the region formed by vertical injection are jointly used for forming a body region of the LDMOS device; and fabricating a source electrode region and a drainage electrode contact region of the LDMOS device, wherein the source electrode region and the drainage electrode contact region adopt second doping different from first doping. The method and device are advantaged by low thermal budget, low on-resistance, and high breakdown voltage.

The invention belongs to the technical field of semiconductor devices and particularly relates to a flexible charge trap storage based on oxidized graphene and a preparation method thereof. According to the flexible charge trap storage and the preparation method, the storage relies on the three-layer structure of an existing charge trap storage, namely, the tunneling layer/charge trap layer/control gate dielectric layer structure, a flexible substrate is utilized as a substrate, and the oxidized graphene is adopted to replace the traditional charge trap layer. The method comprises the specific preparation steps of using a low-temperature atomic layer deposition method, firstly, depositing the dielectric tunneling layer on the flexible substrate, coating the flexible substrate with the oxidized graphene in a rotating mode under the indoor temperature situation, and then, similarly adopting the low-temperature atomic layer deposition technology to grow and control the gate dielectrics. The flexible charge trap storage and the preparation method have the advantages that the low-temperature atomic layer deposition technology and the process of coating the flexible substrate with the oxidized graphene at the indoor temperature in the rotating mode are used, the characteristics of the oxidized graphene is utilized, window erasing is ensured, meanwhile, the process thermal budget is greatly reduced, and practical and reliable schemes are provided for flexible electronic devices in future.

A method for etching an aluminum pad layer comprises providing a semiconductor substrate, forming an aluminum pad layer, a passivating layer and a dielectric layer on the semiconductor substrate, wherein the aluminum layer is inlaid in the passivating layer and exposes through the passivating layer and a first opening of the dielectric layer, and further utilizing argon plasma to etch the aluminum pad layer, wherein the production power (MF) for generating the argon plasma is arranged between 600W and 800W, the accelerating power (RF) for accelerating the argon plasma is arranged between 100W and 600W, and the etching time is arranged between 55s and 100s. The invention further provides a method for forming bumps. Compared with the prior art, the method for etching an aluminum pad layer reduces the generation power (MF) for generating the argon plasma, the accelerating power (RF) for accelerating the argon plasma and the time to etch the aluminum pad layer, thereby avoiding the problem of rough surface of the aluminum pad layer caused by over-etching to the aluminum pad layer in the prior art.

The invention discloses a formation method of an interfacial layer and a formation method of a metal gate transistor. The formation method of the interfacial layer is different from a conventional formation method of an interfacial layer. The formation method of the interfacial layer involves forming a high-K dielectric layer first and then forming the interfacial layer and specifically comprises performing annealing processing in a gas atmosphere containing an oxidation gas, wherein during an annealing process, the oxidation gas with quite high energy in a high temperature environment can penetrate the high-K dielectric layer and is diffused to an interface between the high-K dielectric layer and a substrate so as to be contacted with the substrate, such that the surface, which is contacted with the high-K dielectric layer, of the substrate can be oxidized and the interfacial layer is grown. Since the interfacial layer is formed after the high-K dielectric layer, some defects of the high-K dielectric layer can be restored during the process of forming the interfacial layer, for instance, in the annealing process when the interfacial layer is formed, the oxidation gas can supplement oxygen atoms to the high-K dielectric layer to enable the actual components of the high-K dielectric layer to be more similar to corresponding components in an ideal chemical molecular formula.

The invention discloses a surrounding-gate field effect transistor, which combines a vertical channel and a Schottky barrier source/drain structure. The surrounding-gate field effect transistor comprises a surrounding semiconductor channel (4) in the vertical direction, a surrounding gate electrode (6), a surrounding gate dielectric layer (5), a source region (2), a drain region (3) and a semiconductor substrate (1), wherein the source region (2) is located at the bottom part of the vertical channel (4) and is connected with the substrate (1); the drain region (3) is located at the top part of the vertical channel (4); the gate dielectric layer (5) and the gate electrode (6) surround the vertical channel (4); Schottky contact with the same barrier height is respectively formed between the source region (2) and the drain region (3) and the channel (4); and the source region and the drain region use the same metal material. The structure uses the Schottky barrier source/drain structure so as to reduce thermal budget, reduce serial resistance and parasitic capacitance and simplify technology requirements, and uses the vertical channel and the surrounding gate structure so as to break through limitation of integrated processing lithography limit and improve the degree of integration.

The invention discloses a manufacturing method of a charge trapping non-volatile memory. The method comprises the following steps of: forming an active region and a channel region of a device on a semiconductor substrate through shallow-trench isolation; forming a multi-stack gate medium layer comprising a tunneling layer, a charge storage layer and a barrier layer on the substrate by combining the low-temperature chemical vapor deposition and atomic layer deposition technology, and forming a pattern through photoetching; forming a side wall and a mask layer of the gate medium layer by a low-temperature chemical vapor deposition and photoetching method; forming a source/drain region and an expansion region thereof through ion implantation, and activating by laser; forming a gate electrode on the gate medium layer, and depositing a polycrystalline silicon medium at the upper layer of the gate electrode to form a multi-gate electrode layer; executing the isolation and encapsulation operations of the gate structure by a low-temperature chemical vapor deposition method; and leading out the gate, source and drain electrodes through metal interconnection. Through the invention, the heat budget in the memory manufacturing process can be reduced, and the crystallization problem of the thin-film medium layer of a high-dielectric constant material is inhibited.

The invention relates to a production method of an MOS (Metal Oxide Semiconductor) transistor, which comprises the following steps of: carrying out etching on a first medium layer and a polysilicon layer for the first time to form an auxiliary hard mask layer; oxidizing the polysilicon layer in the auxiliary hard mask layer to form a first oxide layer; injecting for the first time to form high doping source/drain electrodes; removing the first oxide layer; etching the auxiliary hard mask layer to form a polysilicon gate electrode and a gate medium layer; oxidizing the polysilicon gate electrode for the second time to form a second oxide layer; forming first side walls on a semiconductor substrate and two sides of the polysilicon grate electrode; injecting for the second time to form low doping source/drain electrodes and then forming a second medium layer; and annealing. By adjusting the process of the MOS transistor, the high doping source/drain electrodes are formed before the low doping source/drain electrodes are formed, and the high doping source/drain electrodes and the low doping source/drain electrodes are only annealed once, and over-large diffusion area can not be caused by long-time annealing, thereby facilitating the form of ultra shallow junctions.

A surrounding gate field-effect transistor combined with a vertical channel, a core-casing structure and a junction-free structure comprises a surrounding semiconductor core in the vertical direction, a surrounding semiconductor casing in the vertical direction, a surrounding gate electrode, a surrounding gate dielectric layer, a core source region, a core drain region, a casing source region, a casing drain region and a semiconductor substrate, wherein the core source region is located at the bottom of a vertical core channel and connected with the substrate, and the core drain region is located at the top of the vertical core channel. The casing source region is located at the bottom of a vertical casing channel and connected with the substrate, and the casing drain region is located at the top of the vertical casing channel. The casing channel surrounds the core channel circularly. The gate dielectric layer surrounds the casing channel. The gate electrode surrounds the gate dielectric layer. The same impurities are doped into source and drain channels of the transistor, so that heat budget is greatly reduced, the impurity diffusion and abrupt junction forming problems are eliminated, process requirements are simplified, drive current is increased by utilizing a germanium core, integration machining photo-etching ultimate limit is broken through by utilizing the vertical channels and a surrounding gate structure, and the integration degree is improved.

The invention provides a nonvolatile memory, which is positioned on a substrate and comprises a tunneling layer, a charge capture composite layer, a grid and a source electrode/drain electrode area, wherein, the tunneling layer is positioned on the substrate; the charge capture composite layer is positioned on the tunneling layer; the grid is positioned above the charge capture composite layer; and the source electrode/drain electrode area is positioned in the substrate on both sides of the tunneling layer. The nonvolatile memory provided with the charge capture composite layer has good programming and erasing performance and data retaining capability. In addition, the high thermal budget technology is not needed for the formation of the charge capture composite layer, thereby reducing the thermal budget during the technological process.

The provided MOS transistor comprises asymmetric source and drain structures. Wherein, the source uses metal or metal-semiconductor compound and channel to form Schottky barrier contact, while the drain is boost high doped. Compared with traditional MOSFET device, this invention increases on-off current rate greatly, compatible to traditional manufacture technology, and has much room for high-K grid medium and metal grid material since low thermal budget.

Provided is a formation method for an amorphous carbon hard mask layer. The formation method includes that a semiconductor substrate is provided; the initial amorphous carbon hard mask layer is formed on the semiconductor substrate and a reaction temperature for the formation of the initial amorphous carbon hard mask layer is 200 DEG C-300 DEG C; nitrogenous plasma is used for processing the initial amorphous carbon hard mask layer. The formation method of the amorphous carbon hard mask layer forms the amorphous carbon hard mask layer by adopting a low temperature technology, the amorphous carbon hard mask layer with high compactness is formed by the method that the nitrogenous plasma is used for processing the initial amorphous carbon hard mask layer, the heating budget is reduced and stability of a device is improved.

The atomic-layer pulse deposition preparation method for high-density nano-Ru crystal comprises: heat growing SiO2 layer or film with high dielectric constant on the Si surface, depositing 2-5nm Ru film with atomic-layer pulse deposition, and fast annealing at high temperature. This invention is compatible to CMOS technique, and operates simply.