Production method of MOS (Metal Oxide Semiconductor) transistor

Abstract

The invention relates to a production method of an MOS (Metal Oxide Semiconductor) transistor, which comprises the following steps of: carrying out etching on a first medium layer and a polysilicon layer for the first time to form an auxiliary hard mask layer; oxidizing the polysilicon layer in the auxiliary hard mask layer to form a first oxide layer; injecting for the first time to form high doping source/drain electrodes; removing the first oxide layer; etching the auxiliary hard mask layer to form a polysilicon gate electrode and a gate medium layer; oxidizing the polysilicon gate electrode for the second time to form a second oxide layer; forming first side walls on a semiconductor substrate and two sides of the polysilicon grate electrode; injecting for the second time to form low doping source/drain electrodes and then forming a second medium layer; and annealing. By adjusting the process of the MOS transistor, the high doping source/drain electrodes are formed before the low doping source/drain electrodes are formed, and the high doping source/drain electrodes and the low doping source/drain electrodes are only annealed once, and over-large diffusion area can not be caused by long-time annealing, thereby facilitating the form of ultra shallow junctions.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a MOS transistor. Background technique [0002] As the semiconductor industry moves toward smaller and faster devices, the feature lateral dimensions and depths of semiconductor devices are gradually decreasing, and the requirements for device performance are getting higher and higher. [0003] US Patent No. US6512273 discloses a manufacturing method for MOS transistors, by forming polysilicon sidewalls for n-channel transistors and forming silicon nitride sidewalls for p-channel transistors, thereby optimizing the performance of each device. Driving current to improve hot-carrier lifetime of n-channel devices. [0004] The US patent No. US5869379 discloses a method of manufacturing a MOS transistor, which reduces the lateral coupling capacitance between adjacent gate electrodes by forming air spacers on both sides of the polysilicon gate electro...

AI Technical Summary

Problems solved by technology

[0010] In the above-mentioned method of forming a MOS transistor, in order to prevent overrun between the source and the drain and to suppress the short channel effect, the implantation of the source/drain is divided into two steps, that is, low-doped drain implantation and heavily doped source/drain implants

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