How to make a mos transistor

Abstract

A method for manufacturing a MOS transistor, comprising: first etching a first dielectric layer and a polysilicon layer to form an auxiliary hard mask layer; oxidizing the polysilicon layer in the auxiliary hard mask layer to form a first oxide layer; Perform the first implantation to form heavily doped source / drain; remove the first oxide layer; etch the auxiliary hard mask layer to form the polysilicon gate electrode and gate dielectric layer; perform the second oxidation on the polysilicon gate electrode to form the second oxide layer layer; forming first sidewalls on both sides of the polysilicon gate electrode on the semiconductor substrate; performing second implantation to form a low-doped source / drain; forming a second dielectric layer; performing annealing. In the present invention, by adjusting the process of the MOS transistor, the heavily doped source / drain is formed first, and then the lowly doped source / drain is formed, and the heavily doped source / drain and the lowly doped source / drain undergo only one annealing, The diffusion area will not be too large due to annealing for a long time, which is conducive to the formation of ultra-shallow junctions.

Description

technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a method for fabricating a MOS transistor. Background technique [0002] As the semiconductor industry develops toward smaller and faster devices, the lateral size and depth of features of semiconductor devices are gradually decreasing, and device performance requirements are becoming higher and higher. [0003] A manufacturing method of a MOS transistor is disclosed in US Patent No. US6512273, by forming polysilicon sidewalls for N-channel transistors and silicon nitride sidewalls for p-channel transistors, thereby optimizing the performance of each device. Drive current to improve hot carrier lifetime of n-channel devices. [0004] In the US Patent No. US5869379, a manufacturing method of a MOS transistor is disclosed. By forming air spacers on both sides of the polysilicon gate electrode, the lateral coupling capacitance between adjacent gate electrodes is redu...

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Problems solved by technology

[0010] In the above-mentioned method of forming a MOS transistor, in order to prevent overrun between the source and the drain and to suppress the short channel effect, the implantation of the source / drain is divided into two steps, that is, low-doped drain implantation and heavily doped source / drain implants, however, in the above method, the implanted region formed by the low-doped drain implant needs to undergo at least two anneals, and each additional anneal will increase the diffusion area of ​​the implanted ions , it will be difficult to form ultra-shallow junctions and difficult to control lateral diffusion

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