Fabrication method of MOS (Metal Oxide Semiconductor) transistor

Abstract

The invention relates to a fabrication method of an MOS (Metal Oxide Semiconductor) transistor, comprising the steps of: carrying out primary etching on a first dielectric layer and a polysilicon layer to form an auxiliary hard mask layer; oxidizing the polysilicon layer in the auxiliary hard mask layer to form a first oxidation layer; carrying out first injection to form a heavy-doping source / drain electrode; carrying out primary annealing; removing the first oxidation layer; etching the auxiliary hard mask layer to form a polysilicon gate electrode and a gate dielectric layer; carrying out secondary oxidation on the polysilicon gate electrode to form a second oxidation layer; forming first side walls on a semiconductor substrate and two sides of the polysilicon gate electrode; carrying out secondary injection to form a low-doping source / drain electrode; and carrying out secondary annealing. In the invention, by adjusting the fabrication process of the MOS transistor, the heavy-doping source / drain electrode is formed firstly and then the low-doping source / drain electrode is formed, and because the low-doping source / drain electrode is formed in a later phase, and the injection area of the low-doping source / drain electrode is only subjected to one-time annealing, an overlarge diffusion area cannot be formed due to long-time annealing, and a ultra shallow junction can be formed easily.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a MOS transistor. Background technique [0002] As the semiconductor industry moves toward smaller and faster devices, the feature lateral dimensions and depths of semiconductor devices are gradually decreasing, and the requirements for device performance are getting higher and higher. [0003] US Patent No. US6512273 discloses a manufacturing method for MOS transistors, by forming polysilicon sidewalls for n-channel transistors and forming silicon nitride sidewalls for p-channel transistors, thereby optimizing the performance of each device. Driving current to improve hot-carrier lifetime of n-channel devices. [0004] The US patent No. US5869379 discloses a method of manufacturing a MOS transistor, which reduces the lateral coupling capacitance between adjacent gate electrodes by forming air spacers on both sides of the polysilicon gate electro...

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Problems solved by technology

[0010] In the above-mentioned method of forming a MOS transistor, in order to prevent overrun between the source and the drain and to suppress the short channel effect, the implantation of the source / drain is divided into two steps, that is, low-doped drain implantation and heavily doped source / drain implants, however, in the above method, the implanted region formed by the low-doped drain implant needs to undergo at least two anneals, and each additional anneal will increase the diffusion area of ​​the implanted ions , it will be difficult to form ultra-shallow junctions and difficult to control lateral diffusion

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