A MOS resistor and its manufacture method

Abstract

The provided MOS transistor comprises asymmetric source and drain structures. Wherein, the source uses metal or metal-semiconductor compound and channel to form Schottky barrier contact, while the drain is boost high doped. Compared with traditional MOSFET device, this invention increases on-off current rate greatly, compatible to traditional manufacture technology, and has much room for high-K grid medium and metal grid material since low thermal budget.

Description

Technical field: [0001] The invention belongs to the technical field of semiconductor integrated circuits and its manufacture, and in particular relates to a MOS transistor with a new structure and a manufacturing method thereof. Background technique: [0002] In the contemporary information society, driven by the dual drive of chip integration density maximization and circuit performance optimization, the core MOSFET devices of integrated circuits are continuously scaled down. With the continuous shrinking of the size of MOSFET devices, when the feature size of devices enters the nanometer scale, integrated circuits with MOSFETs as the core encounter more and more challenges in many fields such as materials, structures and processes. In order to meet these challenges, many new device structures and process fabrication methods have been proposed and applied to the design and manufacture of nanometer-scale MOSFETs. [0003] Schottky barrier source-drain MOSFET is one of them...

AI Technical Summary

Problems solved by technology

Some researchers have proposed a Schottky barrier source-drain MOSFET with source-drain elevation, that is, a recessed gate. This structure device has a large on-off current ratio, but its source terminal is raised while reducing the device On-state current, and at the same time, there are difficulties in the realization of the device process at the nanometer scale

Some researchers have also proposed that the source end uses metal or metal silicide to form a Schottky barrier, and the drain end uses doping implantation to form a PN junction. This device structure has good device characteristics, but self-alignment cannot be achieved in the process. Simultaneous doping Implantation is done after the gate structure is formed, which means a high thermal budget, making it difficult to apply to nanoscale MOSFET fabrication

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