Semiconductor structure with channel stress layer and forming method thereof

Abstract

The invention provides a semiconductor structure with a channel stress layer and a forming method thereof. The semiconductor structure comprises a substrate, a grid dielectric layer formed on the substrate, a grid formed on the grid dielectric layer, a source and a drain which are formed in the substrate and positioned on two sides of the grid, one or more side walls formed on the grid dielectric layer and two sides of the grid, and an embedded stress layer which is formed below the grid and is positioned in the substrate. Due to the embedded stress layer which is arranged in a channel below the grid, the mobility of a carrier can be effectively improved; therefore, the driving current of a transistor is improved. In addition, lower thermal budget is present in the process flow of forming the embedded stress layer; therefore, the semiconductor structure contributes to keeping a higher stress level in the channel area. Moreover, besides advantage of stress, the embedded stress layer in the channel can reduce boron (B) diffusion / intrusion in heavy-doped source and drain regions.

Description

Technical field [0001] The present invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure formed with a channel stress layer and a method for forming the same. Background technique [0002] The performance and cost requirements of integrated circuits have led to a sharp reduction in the size of integrated circuit components, and the proximity of various devices on the chip has been increasing. As the specifications of integrated circuit components continue to decrease, many improvements have been made to the design of integrated circuit transistors in order to maintain the performance of these components at an appropriate level. For example, lightly doped structure (LDD), halo (halo) doping and graded impurity distribution are used to reduce short channel and breakdown effects. An important factor in maintaining proper performance in a field-effect transistor is carrier mobility, which affects the amount of current or ...

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Problems solved by technology

[0003] The disadvantage of the existing technology is that although the above application discloses a solution to improve the mobility of carriers through stress film coating, although it can improve the mobility of carriers, its structure is complicated and not suitable for the current mainstream technology.

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