Surrounding-gate field effect transistor and fabrication method thereof

Abstract

The invention discloses a surrounding-gate field effect transistor, which combines a vertical channel and a Schottky barrier source/drain structure. The surrounding-gate field effect transistor comprises a surrounding semiconductor channel (4) in the vertical direction, a surrounding gate electrode (6), a surrounding gate dielectric layer (5), a source region (2), a drain region (3) and a semiconductor substrate (1), wherein the source region (2) is located at the bottom part of the vertical channel (4) and is connected with the substrate (1); the drain region (3) is located at the top part of the vertical channel (4); the gate dielectric layer (5) and the gate electrode (6) surround the vertical channel (4); Schottky contact with the same barrier height is respectively formed between the source region (2) and the drain region (3) and the channel (4); and the source region and the drain region use the same metal material. The structure uses the Schottky barrier source/drain structure so as to reduce thermal budget, reduce serial resistance and parasitic capacitance and simplify technology requirements, and uses the vertical channel and the surrounding gate structure so as to break through limitation of integrated processing lithography limit and improve the degree of integration.

Description

technical field [0001] The invention belongs to the field of field effect transistor logic devices and circuits in CMOS ultra-large integrated circuits (ULSI), and in particular relates to a ring gate field effect transistor combined with a vertical channel and a Schottky barrier source / drain structure and a preparation method thereof. Background technique [0002] Driven by Moore's Law, the feature size of traditional MOSFETs has been shrinking, and now it has entered the nanometer scale. As a result, the negative effects of short-channel effects on devices have become more serious. The effects of leakage-induced barrier reduction and band-band tunneling increase the off-state leakage current of the device. In the research on new device structures, the source-drain doped Gate All Around transistor (GAA) structure is currently the most concerned one. GAA devices have better gate control characteristics, which can meet the sharpest characteristic requirements, so as to meet ...

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In addition, the introduction of nanowires makes the source and drain

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