Formation method of interfacial layer and formation method of metal gate transistor

Abstract

The invention discloses a formation method of an interfacial layer and a formation method of a metal gate transistor. The formation method of the interfacial layer is different from a conventional formation method of an interfacial layer. The formation method of the interfacial layer involves forming a high-K dielectric layer first and then forming the interfacial layer and specifically comprises performing annealing processing in a gas atmosphere containing an oxidation gas, wherein during an annealing process, the oxidation gas with quite high energy in a high temperature environment can penetrate the high-K dielectric layer and is diffused to an interface between the high-K dielectric layer and a substrate so as to be contacted with the substrate, such that the surface, which is contacted with the high-K dielectric layer, of the substrate can be oxidized and the interfacial layer is grown. Since the interfacial layer is formed after the high-K dielectric layer, some defects of the high-K dielectric layer can be restored during the process of forming the interfacial layer, for instance, in the annealing process when the interfacial layer is formed, the oxidation gas can supplement oxygen atoms to the high-K dielectric layer to enable the actual components of the high-K dielectric layer to be more similar to corresponding components in an ideal chemical molecular formula.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing, and in particular relates to a method for forming an interface layer and a method for forming a metal gate transistor. Background technique [0002] With the continuous development of semiconductor technology, the feature size of MOS transistors is continuously reduced, and the thickness of the gate dielectric layer of MOS transistors is also becoming thinner and thinner according to the principle of proportional reduction. When the thickness of the gate dielectric layer is thin to a certain extent, its reliability problems, especially problems related to time-related breakdown, hot carrier effect, and diffusion of impurities in the gate electrode to the substrate, will become serious. Affect the stability and reliability of the device. Now, silicon oxide as the gate dielectric layer has reached its physical thickness limit. Using a high-K dielectric layer to replace the silicon oxide ...

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Problems solved by technology

[0003] However, since the high-K dielectric layer is mostly metal ion oxide and has no fixed atomic coordination, the stability of the bond between it and the silicon substrate is worse than that between silicon oxide and the silicon substrate. Many, resulting in a large number of interface defects between the high-K dielectric layer and the silicon substrate

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