Formation method of interfacial layer and formation method of metal gate transistor
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A metal gate and interface layer technology, applied in the manufacture of transistors, semiconductor devices, semiconductor/solid-state devices, etc., can solve problems such as poor stability and interface defects between high-K dielectric layers and silicon substrates
Inactive Publication Date: 2014-10-15
SEMICON MFG INT (SHANGHAI) CORP
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[0003] However, since the high-K dielectric layer is mostly metal ion oxide and has no fixed atomic coordination, the stability of the bond between it and the silicon substrate is w
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[0061] Example one
[0062] Such as figure 1 As shown, first, step S1 is performed: a semiconductor substrate 100 is provided.
[0063] The semiconductor substrate 100 is a commonly used substrate material such as a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The semiconductor substrate 100 can also be doped with germanium, indium arsenide, lead telluride, Materials such as gallium telluride. A shallow trench isolation structure 110 is formed in the semiconductor substrate 100 to isolate the metal gate transistor from other devices formed on the semiconductor substrate 100.
[0064] Continue to refer figure 1 As shown, step S2 is then performed: forming a dummy gate 130 on the semiconductor substrate 100.
[0065] In one embodiment, the method for forming the dummy gate 130 includes: forming an etching stop layer on the semiconductor substrate 100; forming a dummy gate material layer on the etching stop layer, the material of which may be polysilicon or silico...
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[0086] Example two
[0087] Such as Figure 8 As shown, first, step S11 is performed: a semiconductor substrate 200 is provided.
[0088] A shallow trench isolation structure 210 is formed in the semiconductor substrate 200 to isolate the metal gate transistor from other devices formed in the semiconductor substrate 200. For more specific content of this step, reference may be made to step S1 in the first embodiment, which will not be repeated in this embodiment.
[0089] Continue to refer Figure 8 As shown, step S12 is then performed: forming a high-K dielectric layer 220 on the semiconductor substrate 100.
[0090] For the specific material and forming method of the high-K dielectric layer 220, please refer to the first embodiment, which will not be repeated here.
[0091] Continue to refer Figure 8 As shown, step S13 is then performed: an interface layer 230 is formed on the surface of the semiconductor substrate 100 in contact with the high-K dielectric layer 220.
[0092] The met...
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Abstract
The invention discloses a formation method of an interfacial layer and a formation method of a metal gate transistor. The formation method of the interfacial layer is different from a conventional formation method of an interfacial layer. The formation method of the interfacial layer involves forming a high-K dielectric layer first and then forming the interfacial layer and specifically comprises performing annealing processing in a gas atmosphere containing an oxidation gas, wherein during an annealing process, the oxidation gas with quite high energy in a high temperature environment can penetrate the high-K dielectric layer and is diffused to an interface between the high-K dielectric layer and a substrate so as to be contacted with the substrate, such that the surface, which is contacted with the high-K dielectric layer, of the substrate can be oxidized and the interfacial layer is grown. Since the interfacial layer is formed after the high-K dielectric layer, some defects of the high-K dielectric layer can be restored during the process of forming the interfacial layer, for instance, in the annealing process when the interfacial layer is formed, the oxidation gas can supplement oxygen atoms to the high-K dielectric layer to enable the actual components of the high-K dielectric layer to be more similar to corresponding components in an ideal chemical molecular formula.
Description
technical field [0001] The invention belongs to the field of semiconductor manufacturing, and in particular relates to a method for forming an interface layer and a method for forming a metal gate transistor. Background technique [0002] With the continuous development of semiconductor technology, the feature size of MOS transistors is continuously reduced, and the thickness of the gate dielectric layer of MOS transistors is also becoming thinner and thinner according to the principle of proportional reduction. When the thickness of the gate dielectric layer is thin to a certain extent, its reliability problems, especially problems related to time-related breakdown, hot carrier effect, and diffusion of impurities in the gate electrode to the substrate, will become serious. Affect the stability and reliability of the device. Now, silicon oxide as the gate dielectric layer has reached its physical thickness limit. Using a high-K dielectric layer to replace the silicon oxide ...
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