Junction-free field-effect transistor and preparation method thereof

A field-effect transistor and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of complex GAA source-drain design, achieve good modulation effect, improve integration, and simplify the process.

Active Publication Date: 2014-12-10
PEKING UNIV
View PDF4 Cites 13 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, the introduction of nanowires makes the source and drain

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Junction-free field-effect transistor and preparation method thereof
  • Junction-free field-effect transistor and preparation method thereof
  • Junction-free field-effect transistor and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0038] The present invention provides a field effect transistor with a novel structure, specifically a gate-around field effect transistor (such as figure 1 shown), including a ring-shaped semiconductor channel 4 in a vertical direction, a ring-shaped gate electrode 6, a ring-shaped gate dielectric layer 5, a source region 2, a drain region 3, and a semiconductor substrate 1; wherein, the source The region 2 is located at the bottom of the vertical channel 4 and is in contact with the substrate 1. The drain region 3 is located at the top of the vertical channel 4. The gate dielectric layer 5 and the gate electrode 6 surround the vertical channel 4 in a ring shape; the source region 2 and the The drain region 3 and the channel 4 are doped with the same type and concentration of impurities.

[0039] Doping impurity concentration is higher, generally should be 10 19 -10 20 cm -3 above.

[0040] Specific examples of the preparation method of the present invention include Fig...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

A surrounding gate field-effect transistor combined with a vertical channel (4) and a junction-free structure comprises a surrounding semiconductor channel in the vertical direction, a surrounding gate electrode (6), a surrounding gate dielectric layer (5), a source region (2), a drain region (3) and a semiconductor substrate (1), wherein the source region (2) is located at the bottom of the vertical channel (4) and connected with the substrate (1), the drain region (3) is located at the top of the vertical channel (4), and the gate dielectric layer (5) and the gate electrode (6) surround the vertical channel (4) circularly. The impurities of the same type and concentration are doped into the source region (2), the drain region (3) and the vertical channel (4). The same impurities are doped into source and drain channels of the transistor, so that heat budget is greatly reduced, the impurity diffusion and abrupt junction forming problems are eliminated, process requirements are simplified, integration machining photo-etching ultimate limit is broken through by utilizing the vertical channel and a surrounding gate structure, and the integration degree is improved.

Description

technical field [0001] The invention belongs to the field of field effect transistor logic devices and circuits in CMOS ultra large integrated circuits (ULSI), and in particular relates to a ring gate field effect transistor combined with a vertical channel and a junctionless structure and a preparation method thereof. Background technique [0002] Driven by Moore's Law, the feature size of traditional MOSFETs has been shrinking, and now it has entered the nanometer scale. As a result, the negative effects of short-channel effects on devices have become more serious. The effects of leakage-induced barrier reduction and band-band tunneling increase the off-state leakage current of the device. In the research on new device structures, the source-drain doped Gate All Around transistor (GAA) structure is currently the most concerned one. GAA devices have better gate control characteristics, which can meet the sharpest characteristic requirements, so as to meet the needs of devi...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H01L29/10H01L21/336
CPCH01L29/1037H01L29/66477H01L29/78
Inventor 孙雷徐浩张一博韩静文王漪张盛东
Owner PEKING UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap