Two-dimensional negative quantum capacitance transistor device and preparation method thereof

Abstract

The invention discloses a two-dimensional negative quantum capacitance transistor device and a preparation method thereof. The two-dimensional negative quantum capacitance transistor device comprises a substrate; a buried gate which is formed in the substrate, wherein the upper surface of the buried gate is flush with the upper surface of the substrate; a third-generation topological insulator layer which is formed on the buried gate, wherein the length of the third-generation topological insulator layer is equal to that of the buried gate; a high-K dielectric layer which covers the third-generation topological insulator layer; a two-dimensional channel layer which is formed on the high-K dielectric layer, wherein the two-dimensional channel layer and the third-generation topological insulator layer have a common area; a source electrode and a drain electrode which are formed on the substrate and the two sides of the two-dimensional channel layer respectively, partially cover the two-dimensional channel layer and are not overlapped with the buried gate, wherein the topological insulator layer provides negative quantum capacitance, so the total capacitance of the gate is increased, and the sub-threshold swing is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a two-dimensional negative quantum capacitance transistor device and a preparation method thereof. Background technique [0002] With the further scaling down of the feature size of semiconductor devices, the ever-increasing power consumption in complementary metal-oxide-semiconductor (CMOS) circuits has become an urgent problem to be solved. [0003] As the device size decreases, the operating voltage needs to be reduced to reduce power consumption. However, the reduction of the operating voltage is limited by the Boltzmann limit. In order to solve this problem, some novel devices with subthreshold swing (SS) below 60mV / dec at room temperature have been proposed, such as the negative capacitance field effect Transistor (NCFET) for low-power operation through an internal voltage amplification mechanism. [0004] The traditional negative capacitance effect oc...

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Problems solved by technology

[0004] The traditional negative capacitance effect occurs during the polarization reversal of ferroelectric materials. However, the ferroelectric reversal rate is slow (the reversal time is usually 100-200ps), and the switching speed of the device is not very ideal and is subject to hysteresis behavior.

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