Knot-free nanowire field effect transistor

A technology of field-effect transistors and nanowires, which is applied in semiconductor devices, electrical components, circuits, etc., can solve problems such as the difficulty of forming devices, and achieve increased on-state current, increased speed, and weakened leakage-induced barrier reduction effects. Effect
CN102544073AInactive Publication Date: 2012-07-04PEKING UNIV SHENZHEN GRADUATE SCHOOL +1
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
PEKING UNIV SHENZHEN GRADUATE SCHOOL
Publication Date
2012-07-04
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention discloses a knot-free nanowire field effect transistor which comprises a channel, a source region and a drain region. The source region is arranged at one end of the channel, and the drain region is arranged at the other end of the channel; the outer surface of the channel is covered by a gate oxide layer which is covered by a grid electrode layer; and the grid electrode layer comprises a first grid electrode layer which is close to the source region and a second grid electrode layer which is close to the drain region. Compared with the prior art, the embodiment of the invention has the advantages that: by adopting a split gate structure, the speed of the charge carrier in the channel of the knot-free nanowire field effect transistor is increased, so the on-state current is increased, the off-state current of a device is reduced irrespective of the influence of the threshold voltage, the influence of the drain region on the device is screened, the drain induced barrier lowering effect is obviously weakened and the driving ability of the current is improved. Meanwhile, with the split gate, the transconductance feature of the knot-free nanowire field effect transistor under low voltage is obviously improved.
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Description

technical field

[0001] The invention belongs to the technical field of semiconductors, in particular to a split-ring gate junction-free nanowire field-effect transistor. Background technique

[0002] The development of integrated circuits has been guided by Moore's Law, making integrated circuits higher density, lower power consumption, and more functions that can be realized, all of which are inseparable from device size reduction and performance improvement. However, with the continuous shrinking of the device size, especially when the device enters the deep nanoscale, various secondary effects of the device, such as short channel effect, leakage-induced barrier lowering effect, etc., lead to the degradation of device performance. Therefore, in order to suppress adverse effects such as short channels and improve device performance, many new device structures have been continuously proposed, such as double-gate devices, triple-gate devices, fin field effect transistors, and...

Claims

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