197results about How to "Shielding effect" patented technology

A thermally enhanced semiconductor package with EMI (electric and magnetic interference) shielding is provided in which a chip is mounted on and electrically connected to a surface of a substrate, and a thermally conductive member is stacked on the chip and electrically coupled to the surface of the substrate by bonding wires. An encapsulant is formed and encapsulates the chip, thermally conductive member, and bonding wires. A plurality of solder balls are implanted on an opposite surface of the substrate. The thermally conductive member is grounded via the bonding wires, substrate, and solder balls, and provides an EMI shielding effect for the chip to protect the chip against external electric and magnetic interference. The thermally conductive member has a coefficient of thermal expansion similar to that of the chip, and reduces thermal stress exerted on the chip and enhances mechanical strength of the chip to thereby prevent chip cracks.

The invention discloses a pixel unit, an array substrate, a liquid crystal panel, a display device and manufacturing methods thereof, relating to the technical field of liquid crystal display and aiming to improve a pixel aperture opening ratio, reduce the power consumption and improve the display effect. The pixel unit comprises a thin film transistor, a pixel electrode and a common electrode; the thin film transistor comprises a grid electrode, a grid insulating layer arranged on the grid electrode, an active layer arranged on the grid insulating layer, a source electrode and a drain electrode arranged on the active layer, and a passivation layer arranged on the source electrode and the drain electrode, wherein the common electrode is directly arranged on the passivation layer; and the pixel electrode is arranged below the passivation layer and is connected with the drain electrode of the thin film transistor. According to the array substrate, the liquid crystal panel, the display device and the manufacturing methods thereof, a visual angle can be improved, the power consumption is reduced, the aperture opening ratio is improved and further the display quality can be improved. The pixel unit, the array substrate, the liquid crystal panel and the display device can be used for liquid crystal display.

The invention discloses a method for mapping a mobile virtual network based on clustering. The method for mapping the mobile virtual network based on the clustering aims to improve the mapping success rate from a virtual network to a mobile physical network and virtual network revenue and to reduce mapping overhead. The method for mapping the mobile virtual network based on the clustering takes the physical network clustering as a basis and solves the problems that nodes and links in the process of virtual network mapping and in the process of resource allocation are poor in coordination, and algorithm performance is poor when virtual network topology is sparse in a mobile network environment. The method for mapping the mobile virtual network based on the clustering comprises the following steps: according to the displacement law of the nodes, predicting stability of the links among the nodes, clustering the physical network accordingly, and dividing the virtual network mapping into an inter-cluster mapping mode and an inside-cluster mapping mode. According to the method for mapping the mobile virtual network based on the clustering, due to the fact that a clustering method based on node prediction and the inter-cluster and the inside-cluster mapping modes based on the clustering are introduced, the virtual network mapping can achieve efficient and high success rate of request for the virtual network in the mobile network environment as well.

The invention discloses a three-frequency-range common-caliber active navigation antenna, for solving the problems of not wide enough work frequency band of a conventional navigation antenna, low radiation efficiency and low elevation angle gain of a directional diagram. The three-frequency-range common-caliber active navigation antenna comprises a common-caliber antenna unit (1), a filter (2), a low-noise amplifier (3) and a back cavity (4). The common-caliber antenna unit (1) comprises a high-frequency radiator, an intermediate frequency radiator and a low frequency radiator, the three radiators are successively laminated from top to bottom, and the high frequency radiator and the low frequency radiator employ capacitance coupling feed and introduce parasitic patches; the filter (2) and the low-noise amplifier (3) are disposed below the common-caliber antenna unit (1) and are installed in the cavity of the back cavity (4); and the common-caliber antenna unit (1), the filter (2) and the low-noise amplifier (3) are successively connected. The three-frequency-range common-caliber active navigation antenna can realize multiplexing of antennas of three system frequency ranges and also has the advantages of wide work frequency band and good radiation characteristic, thereby being applied to reception of signals of a satellite navigation system.

The embodiment of the invention provides a service processing method and device. The method comprises the steps of obtaining a service operation request; wherein the service operation request comprises a service field; determining a target operation database according to the service field, and obtaining a plurality of micro-service instances connected with the target operation database, determining a target micro-service instance from the plurality of micro-service instances, and sending the service operation request to the target micro-service instance, so that the target micro-service instance executes corresponding operation on the target operation database according to the service operation request to generate a processing result; and receiving a processing result returned by the target micro-service instance, realizing decoupling of the service logic code and the database operation code, shielding the influence of the database operation code on the service logic code to a great extent, and reducing the redundancy of the service logic code.

The invention discloses a multilayer composite membrane passivation structure of a table top high-power semiconductor device. The multilayer composite membrane passivation structure comprises P-type boron junction areas and an N-type phosphorus junction area, the upper end and the lower end of the N-type phosphorus junction area are provided with the P-type phosphorus areas respectively, and an alpha-polycrystalline silicon layer, a semi-insulating polycrystalline silicon thin membrane, a low-temperature heat oxidation layer, a high-temperature Si3N4 thin membrane, a negative charge glass passivation layer and a low-temperature heat oxidation layer are sequentially arranged on the surface of a PN junction of a table top of the table top high-power semiconductor device from inside to outside. A manufacturing technology of the multilayer composite membrane passivation structure of the table top high-power semiconductor device includes the following steps: a, depositing the alpha-polycrystalline silicon, b, depositing semi-insulating polycrystalline silicon, c, depositing the low-temperature heat oxidation layer, d, depositing Si3N4, e, conducting passivation on glass, and f, depositing the low-temperature heat oxidation layer in the outmost layer. The multilayer composite membrane passivation structure and the manufacturing technology have the advantages that the alpha-polycrystalline silicon layer is deposited, so that crystal lattice adaptation can be achieved, damage to crystal lattices of a silicon wafer in a groove can be repaired, leaked currents in the surfaces of junctions are reduced, and the stability and the reliability of the device at the high temperature are improved.

An electrical connector provided in the present invention comprises a circuit board and a connecting wire member. The circuit board includes an upper circuit layer, a lower circuit layer, and a shielding layer. The connecting wire member includes a plurality of upper wires and a plurality of lower wires. The upper circuit layer has an upper concave portion made by removing circuit, and the lower circuit layer has a lower concave portion made by removing circuit. The upper wire set is disposed in the upper concave portion, and the lower wire set is disposed in the lower concave portion. Thus, the shielding between the upper wire set and the lower wire set is achieved, and the assembling and processing of wires and circuit layer is easier.

The invention provides a double-graphene-layer tunneling field effect transistor. A bottom gate dielectric layer is located on a bottom gate electrode. A double-graphene-layer active area is located on the bottom gate dielectric layer. A metal source electrode and a metal drain electrode are located at the two ends of the double-graphene-layer active area respectively and respectively cover a part of the double-graphene-layer active area. The metal source electrode and the metal drain electrode are made of different materials. For an n-type device, the work function of the metal source electrode is larger, the graphene in contact with the metal source electrode is in p-type doping, the work function of the metal drain electrode is small, and the graphene in contact with the metal drain electrode is in n-type doping. The electrodes of a p-type device are opposite to those of the n-type devices. The metal source electrode, the metal drain electrode and the graphene between the metal source electrode and the metal drain electrode are covered with a top gate dielectric layer. A top gate electrode is located on the top gate dielectric layer and overlaps the metal source electrode and the metal drain electrode. The manufacturing technology of the double-graphene-layer tunneling field effect transistor is simple. Compared with a traditional double-graphene-layer field effect transistor, the metal source electrode and the metal drain electrode of the double-graphene-layer tunneling field effect transistor are completed independently.

The invention relates to a device and method for testing medium material radiation induction conductivity for a satellite, and belongs to the field of testing. The device and method for testing the medium material radiation induction conductivity for the satellite is applicable to a test on thicker medium material radiation induction conductivity in an electrification effect evaluation inside the satellite. The device comprises a shielding box body, a 60Co irradiation source, a vacuum-pumping system, an upper electrode plate, a lower electrode plate, a sample table, an electrometer, a stabilized voltage source, a titanium window and a vacuum box. The method comprises the steps of utilizing the 60Co irradiation source to generate gamma ray irradiation medium materials, meanwhile utilizing the stabilized voltage source to exert voltage on electrodes on the medium materials, testing a leakage current of the lower electrode plate through the electrometer, obtaining a voltage value V and a current value I of the surface of the medium materials, and further calculating to obtain radiation induction conductivity of the medium materials. The device and method for testing the medium material radiation induction conductivity for the satellite is applicable to the test on the thicker medium material radiation induction conductivity in the electrification effect evaluation inside the satellite.

The invention discloses a multi-temperature zone calibration method based on an internal hollow type temperature control member. A multi-segment broken line relationship of temperatures varying along with the light intensity ratio of anti-Stokes to Stokes is obtained by utilizing a segmentation calibration manner while adopting an internal hollow type copper cylinder as the main body of a temperature control system, so that a temperature calibration curve infinitely approaches an index changing curve of the light intensity ratio of anti-Stokes to Stokes and the temperature. Under the precondition that the method does not influence the system performance, the temperature measurement accuracy of a system is further improved, the applicable temperature measurement range of the system is extended, and the defects and disadvantages of an existing temperature calibration manner are better overcome.

The invention discloses an online statistical analysis technique for generator set primary frequency modulation performance abnormity. The method comprises the following steps: selecting typical primary frequency modulation events beneficial for improving precision through generator PMU measured data obtained online, calculating primary frequency modulation contribution rate of a corresponding set, calculating actually measured average speed change rate by adopting an integral algorithm, screening out reasonable primary frequency modulation performance evaluation results by using a reasonable data range and normal distribution variance, and shielding the influences of disturbance and secondary frequency modulation on primary frequency modulation performance evaluation; and then giving an alarm for primary frequency modulation abnormity of the set according to the difference between the two indexes and a reasonable value and a preset value and the change relative to historical value. Operating personnel can discover the generator sets with the problem of primary frequency modulation in time according to the calculation results and alarm information, good primary frequency modulation performance of the generator sets can also be promoted to be maintained, and safe and stable operation of grid frequency is maintained together.

The invention discloses a knot-free nanowire field effect transistor which comprises a channel, a source region and a drain region. The source region is arranged at one end of the channel, and the drain region is arranged at the other end of the channel; the outer surface of the channel is covered by a gate oxide layer which is covered by a grid electrode layer; and the grid electrode layer comprises a first grid electrode layer which is close to the source region and a second grid electrode layer which is close to the drain region. Compared with the prior art, the embodiment of the invention has the advantages that: by adopting a split gate structure, the speed of the charge carrier in the channel of the knot-free nanowire field effect transistor is increased, so the on-state current is increased, the off-state current of a device is reduced irrespective of the influence of the threshold voltage, the influence of the drain region on the device is screened, the drain induced barrier lowering effect is obviously weakened and the driving ability of the current is improved. Meanwhile, with the split gate, the transconductance feature of the knot-free nanowire field effect transistor under low voltage is obviously improved.

The invention provides a method for lowering the influence of reverse current on a battery voltage-resistant insulation test. The method includes the steps that test voltage, test time and insulation-resistance resistance valve qualified standards of the voltage-resistant insulation test are determined according to the nominal capacity of a battery to be tested, and the battery to be tested is the battery which is welded but not subjected to electrolyte injection; the voltage-resistant insulation test is conducted on the battery to be tested by the adoption of the determined test voltage in the determined test time; the result of the voltage-resistant insulation test of the battery to be tested is evaluated according to the determined insulation-resistance resistance valve qualified standard. According to the method, different test voltage, test time and insulation-resistance resistance valve qualified standards are set at the voltage-resistant insulation test stage targeted to batteries to be tested of different nominal capacities, and the influence of the reverse current on the battery voltage-resistant insulation test can be effectively shielded, so that test accuracy is improved, the number of qualified batteries is increased, and the reject ratio is lowered.

The invention discloses a distribution network fault positioning method based on a Bayes formula algorithm. The method comprises fault loop determination and switch saliency calculation. For an area with a high power distribution network automation level, an accurate position of a power distribution network fault is finally determined based on fault information returned by a FTU and a SCADA system and a Bayes formula distribution network fault positioning algorithm. Firstly, based on a GIS geometric network, according to fault information, network topology analysis is performed and a complete fault loop is determined so as to reduce a calculation range. And then, saliency of each measurement and control switch in the fault loop is calculated so as to position to a fault area. Based on the fault information returned by the FTU and the SCADA system and a Bayes formula algorithm theory, a set of scientific and systematic power distribution network fault positioning method is established.

The invention relates to the field of embedded technology, in particular to a system and a method for mapping a C language structure to a relation database table. The invention discloses a system for mapping the C language structure to the relation database table, which simplifies the conversion from the C language structure to the relation database table. The system for mapping the C language structure to the relation database table comprises a mapping code generation engine module from the C language structure to the relation database table, a mapping extendable mark language describing module from the C language structure to the relation database table and a use module of a mapping code from the C language structure to the relation database table. The invention also provides a method for mapping the C language structure to the relation database table. The invention simplifies the cockamamie data management, shields the influence of the change of a lower-layer database on the upper-layer application simultaneously and improves the transferability of the application.

This invention discloses a kind of simple output window. In the microwave window that is sealed with vacuum rubber band, dielectric sheet with metal layer replaces general dielectric sheet without metal layer and uses as window sheet. When dielectric window sheet with metal layer and rubber band are pressed firmly, it is also vacuum sealing functioned. The dielectric sheet with metal layer and window flange of slot positioned rubber band are firmly electric-contacted, it makes shielded rubber band influences electromagnetic field. The metal layer in dielectric window sheet corresponding waveguide inner cross section part is eat off beforehand so as to ensuring that microwave can pass. When using dielectric sheet without metal layer as window sheet, the coefficient of standing wave increases because the existence of rubber band equivalently increases the size of dielectric sheet. In order to decrease the coefficient of standing wave, the size of window sheet must be decreased. It makes rubber band can not be pressed firmly. This invention is simple, low-cost and low-wasting. The coefficient of standing wave is small.