Double-graphene-layer tunneling field effect transistor and manufacturing method thereof

Abstract

The invention provides a double-graphene-layer tunneling field effect transistor. A bottom gate dielectric layer is located on a bottom gate electrode. A double-graphene-layer active area is located on the bottom gate dielectric layer. A metal source electrode and a metal drain electrode are located at the two ends of the double-graphene-layer active area respectively and respectively cover a part of the double-graphene-layer active area. The metal source electrode and the metal drain electrode are made of different materials. For an n-type device, the work function of the metal source electrode is larger, the graphene in contact with the metal source electrode is in p-type doping, the work function of the metal drain electrode is small, and the graphene in contact with the metal drain electrode is in n-type doping. The electrodes of a p-type device are opposite to those of the n-type devices. The metal source electrode, the metal drain electrode and the graphene between the metal source electrode and the metal drain electrode are covered with a top gate dielectric layer. A top gate electrode is located on the top gate dielectric layer and overlaps the metal source electrode and the metal drain electrode. The manufacturing technology of the double-graphene-layer tunneling field effect transistor is simple. Compared with a traditional double-graphene-layer field effect transistor, the metal source electrode and the metal drain electrode of the double-graphene-layer tunneling field effect transistor are completed independently.

Description

technical field [0001] The invention belongs to the technical field of nanoelectronics, and in particular relates to a double-layer graphene tunneling field-effect transistor based on metal contact doping and a preparation method thereof. Background technique [0002] As the feature size of conventional MOSFETs decreases, the operating and threshold voltages of the devices gradually decrease. Since the subthreshold slope of the MOSFET is limited by the thermal potential, there is a theoretical limit of 60mV / dec, which cannot be reduced with the reduction of the device size, so the leakage current of the device increases with the reduction of the operating voltage. In addition, the short-channel effect of small-sized devices is more obvious, and the leakage-induced barrier reduction and source-drain band-band tunneling will further increase leakage current and power consumption. At present, the problem of power consumption has become a key concern in the design of small-scal...

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Problems solved by technology

However, the on-state current of TFET is limited by the low tunneling proba

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