Multilayer composite membrane passivation structure of table top high-power semiconductor device and manufacturing technology of multilayer composite membrane passivation structure of table top high-power semiconductor device

Abstract

The invention discloses a multilayer composite membrane passivation structure of a table top high-power semiconductor device. The multilayer composite membrane passivation structure comprises P-type boron junction areas and an N-type phosphorus junction area, the upper end and the lower end of the N-type phosphorus junction area are provided with the P-type phosphorus areas respectively, and an alpha-polycrystalline silicon layer, a semi-insulating polycrystalline silicon thin membrane, a low-temperature heat oxidation layer, a high-temperature Si3N4 thin membrane, a negative charge glass passivation layer and a low-temperature heat oxidation layer are sequentially arranged on the surface of a PN junction of a table top of the table top high-power semiconductor device from inside to outside. A manufacturing technology of the multilayer composite membrane passivation structure of the table top high-power semiconductor device includes the following steps: a, depositing the alpha-polycrystalline silicon, b, depositing semi-insulating polycrystalline silicon, c, depositing the low-temperature heat oxidation layer, d, depositing Si3N4, e, conducting passivation on glass, and f, depositing the low-temperature heat oxidation layer in the outmost layer. The multilayer composite membrane passivation structure and the manufacturing technology have the advantages that the alpha-polycrystalline silicon layer is deposited, so that crystal lattice adaptation can be achieved, damage to crystal lattices of a silicon wafer in a groove can be repaired, leaked currents in the surfaces of junctions are reduced, and the stability and the reliability of the device at the high temperature are improved.

Description

technical field [0001] The invention relates to a multilayer composite film passivation structure of a mesa high-power semiconductor device, and also relates to a preparation process of the multilayer composite film passivation structure of a mesa high-power semiconductor device. Background technique [0002] In order to prevent surface contamination, it is usually necessary to cover the surface of the semiconductor device with a protective dielectric film to form a passivation layer. The passivation process of high-voltage and high-power semiconductor devices on the mesa generally adopts single-layer glass passivation. Glass passivation can effectively prevent the pn junction contamination on the mesa, and as a terminal structure, improve the surface breakdown characteristics of high-voltage devices on the mesa, so that high-voltage semiconductor devices can obtain Voltage blocking capability. However, the single-layer glass passivation process has inconsistent thermal exp...

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Problems solved by technology

However, the single-layer glass passivation process has inconsistent thermal expansion coefficients between glass and silicon wafers, which easily leads to chip breakage under thermal stress, and glass is an insulating medium, which cannot shield the external electric field and cannot modulate the surface electric field of the pn junction on the table. Boron-containing glass The semiconductor will also be doped to make the device low breakdown, so the passivation effect is limited, and the reliability of single-layer glass passivated high-voltage devices working und

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