Tunneling field effect transistor
一种隧穿场效应、晶体管的技术,应用在半导体器件、电气元件、电路等方向,达到增大开态电流、增加隧穿的几率、良好电流驱动能力的效果
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Embodiment 1
[0044] When the first source region, the second source region, the connection region and the drain region are cuboids, and the number of gate electrode layers is two layers, the formed tunneling field effect transistor is as follows: Figure 1~2 As shown, in this embodiment, the Figure 1~2 The shown double-gate tunneling field effect transistor is called a parallel structure double-gate field effect transistor. figure 1 is a cross-sectional view of a parallel-structure double-gate tunneling field-effect transistor along a first direction, figure 2 It is a perspective view of a double-gate tunneling field effect transistor with a parallel structure. The parallel structure double gate tunneling field effect transistor comprises a gate electrode layer 101, a gate dielectric layer 102, a first source region 103, an inner layer source region 104, an outer layer source region 105, a high resistance region 106, an extension region 107 and a drain region 108 .
[0045] The gate e...
Embodiment 2
[0066] Please refer to Figure 9-10 , in this example, the Figure 9-10 The shown double-gate tunneling field effect transistor is called a vertical structure double-gate tunneling field effect transistor. Figure 9 is a cross-sectional view of a vertical double-gate tunneling field effect transistor along a first direction, Figure 10 It is a perspective view of a vertical double-gate tunneling field effect transistor.
[0067] refer to figure 1 and Figure 9 It can be seen that the structure of the parallel structure and the vertical structure double-gate tunneling field effect transistor is basically the same, including the gate electrode layer 201, the gate dielectric layer 202, the first source region 203, the inner layer source region 204, the outer layer source region 205, the high The blocking region 206 , the extension region 207 , the drain region 208 , and the vertical double-gate tunneling field effect transistor further includes a substrate 209 , and the subst...
Embodiment 3
[0070] When the first source region, the second source region, the connection region and the drain region are cuboids, and the number of gate electrode layers is three layers, the formed tunneling field effect transistor is as follows: Figures 11 to 14 as shown, Figure 11 It is a perspective view of a tri-gate tunneling field effect transistor, Figure 12 is a cross-sectional view of the second source region of the tri-gate tunneling field effect transistor along the second direction, Figure 13 is a sectional view of the connection region of the tri-gate tunneling field effect transistor along the second direction, Figure 14 is a cross-sectional view of the tri-gate tunneling field effect transistor along the first direction.
[0071] Such as Figures 11 to 14 As shown, the tri-gate tunneling field effect transistor in this embodiment also includes an insulating layer 309 and a substrate layer 310; the insulating layer 309 covers the substrate layer 310 in the second di...
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