35results about How to "Large tunneling area" patented technology

The invention provides a low-power consumption tunneling field effect transistor (TFET), belonging to the field of a field effect transistor logic device and a circuit of CMOS (complementary metal oxide semiconductors) ultra large scale integrated circuit (ULSI). The TFET provided by the invention comprises a source, a drain and a control grid, wherein the control grid extends towards a source electrode end into a fork structure, and the fork-structure control grid is composed of an extended grid region and an original control grid region; and the active region which is covered below the extended grid region is similarly a channel region and is made of a substrate material. According to the invention, the channel is enclosed by the source region of the TFET, and the conduction current of the device is improved; and compared with the existing panel TFET, the TFET has provided by the invention has the advantage that under the conditions of the same technology and the same active region size, higher conduction current and a steep subthreshold gradient can be obtained.

The invention provides a multiple source MOS (metal oxide semiconductor) transistor with impurity segregation and a production method thereof. The multiple source MOS transistor comprises a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region; one end of a control gate extends towards the highly-doped sourceregion to form a T shape; the extended gate region is used as an extension gate; an original control gate region is a main gate; the highly-doped source region is formed by highly doping a semiconductor and is positioned on two sides of the extension gate along the width direction of the source region; and one side of the highly-doped region, which is away from the channel direction, is connectedwith a Schottky source region with impurity segregation. Compared with the present MOSFET (metal-oxide-semiconductor field-effect transistor), under the same process condition and the same size of the active region, higher conducting current, lower leakage current and steeper sub-threshold slope can be obtained.

The invention discloses a junction-modulated type tunneling field effect transistor and a manufacturing method of the junction-modulated type tunneling field effect transistor, and belongs to the field of field effect transistor logic devices and circuits in CMOS ultra large scale integration (ULSI) circuits. According to the junction-modulated type tunneling field effect transistor, a PN junction provided by a highly-doped source region enclosed on three sides in a vertical channel region is utilized so that the channel region can be effectively used up, a surface channel energy band below a grid can be increased, a device can obtain a steeper energy band and a smaller tunneling barrier width compared with a traditional TFET when subjected to band-band tunneling, the effect of a steep tunnel junction doping density gradient is achieved equivalently, as a result, the subthreshold property of the traditional TFET is improved substantially, and breakover currents of the device are increased at the same time. According to the junction-modulated type tunneling field effect transistor and the manufacturing method of the junction-modulated type tunneling field effect transistor, under the condition that the junction-modulated type tunneling field effect transistor is compatible with an existing CMOS process, the bipolar breakover effect of the device is restrained effectively, parasitic tunneling currents at corners of a source junction with a small size also can be restrained, and the effect of steep source junction doping density can be achieved equivalently.

The invention discloses a Schottky barrier metal oxide semiconductor (MOS) transistor, which comprises a ring-shaped gate electrode (3), a ring-shaped gate dielectric layer (2), a ring-shaped gate electrode side wall (4), a semiconductor substrate, a source region (5) and a ring-shaped drain region (6). The Schottky barrier MOS transistor is characterized in that: the semiconductor substrate is provided with a convex step structure; the source region is positioned on a high plane of a convex step; the ring-shaped drain region surrounds the convex step and is positioned on a low plane; the gate dielectric layer and the gate electrode are positioned at a corner of the convex step, surrounds the step and is raised into a ring shape; and the gate electrode side wall is ring-shaped, surrounds on the outer side of the gate electrode and has a certain thickness to serve as a shelter to form an underlap structure of a drain terminal. The Schottky barrier MOS transistor adopts a step structurecombining a ring-shaped gate structure and an asymmetric source / drain structure, so on the basis of inheriting advantages of traditional SB-MOSFET, the on-state conduction current is improved, a dipolar effect is inhibited, and the process is simplified.

The invention discloses a tunneling field-effect transistor with a composite-mechanism strip-type grid and a preparation method of the tunneling field-effect transistor and belongs to the field of logic devices and circuits of field-effect transistors in CMOS (Complementary Metal Oxide Semiconductor) ultra-large-scale integrated (ULSI) circuits. The tunneling field-effect transistor has the advantages that the energy band of surface channels under the grid can be improved by changing the shape of the grid and utilizing a depletion effect of PN nodes on the two sides of the strip-type grid, and the subthreshold characteristic of the device is improved; since a composite mechanism is introduced into double-doped source areas, an ON state current of the device is improved; due to an I-shaped design of an active area, body leakage currents, including a source-drain direct tunneling current and a punching current, between the two doped source areas to a doped drain area can be greatly inhibited, and a short-channel effect is inhibited, so that the device with small size can be applied.

The invention provides a tunneling field effect transistor (TFET) with a T-shaped grid structure and low power consumption, and belongs to the field of field effect transistor logic devices and circuits in complementary metal oxide semiconductor (CMOS) ultra large scale integrated circuits (ULSI). The TFET comprises a source electrode, a drain electrode and a control grid, wherein the control grid extends toward the end of the source electrode to form a T shape; the T-shaped control grid consists of an extending grid region and the original control grid region; and an active region covered below the extending grid region is a channel region and is made of a substrate material. By using the T-shaped grid structure, the source region of the TFET encircles a channel, so that the conduction current of a device is improved. Compared with the conventional planar TFET, the TFET can achieve higher conduction current and steeper subthreshold slope under the same process conditions and the samesize of the active region.

The invention provides a low-power consumption tunneling field effect transistor (TFET), belonging to the field of a field effect transistor logic device and a circuit of CMOS (complementary metal oxide semiconductors) ultra large scale integrated circuit (ULSI). The TFET provided by the invention comprises a source, a drain and a control grid, wherein the control grid extends towards a source electrode end into a fork structure, and the fork-structure control grid is composed of an extended grid region and an original control grid region; and the active region which is covered below the extended grid region is similarly a channel region and is made of a substrate material. According to the invention, the channel is enclosed by the source region of the TFET, and the conduction current of the device is improved; and compared with the existing panel TFET, the TFET has provided by the invention has the advantage that under the conditions of the same technology and the same active region size, higher conduction current and a steep subthreshold gradient can be obtained.

The invention discloses a Z-type heterojunction tunneling field effect transistor having a lightly-doped drain structure and a preparation method thereof, and mainly solves the problems of low on-state current and severe bipolar effect of an existing device. The Z-type heterojunction tunneling field effect transistor comprises an SOI substrate (1), isolation grooves (2), a source region (3), a channel region (4), a drain region (6), a gate region (5) and a conductive layer (7). The isolation grooves (2) are arranged at the two sides of the SOI substrate (1); the source region (3), the channelregion (4) and the drain region (6) are arranged on the upper surface of the SOI substrate; the gate region (5) is arranged on the upper side of the channel region (4); the source region (3) adopts agermanium semiconductor; the gate region (5) adopts a Z-type structure, and gates with the length of 3nm-9nm are covered on the source region; and the side, close to the gate region (5), of the drainregion (6) is provided with a lightly-doped drain region. The Z-type heterojunction tunneling field effect transistor can effectively suppress the bipolar effect and improve driving current, and can be used for manufacturing of a large-scale integrated circuit.

The present invention discloses a method for preparing a tunneling field effect transistor, belonging to the field of field effect transistor logic devices in a CMOS super-large-scale integration (ULSI) circuit. The tunneling field effect transistor of an ultra-steep source junction is realized through preparation process design. The device characteristic can be improved significantly, at the same time, the preparation method is compatible with standard CMOS IC technology, TFET devices can be effectively integrated in a CMOS integrated circuit, a low power consumption integrated circuit formed by TFET can be prepared by using standard process, the production cost is greatly reduced, and the process flow is simplified.

The invention provides a tunneling field effect transistor and a preparation method thereof. The preparation method at least comprises the following steps that an SOI substrate provided with top layer silicon, an oxygen buried layer and bottom layer silicon is provided, and ion injection is conducted on the two sides of the top layer silicon to form a source electrode and a drain electrode respectively; an intrinsic silicon layer, and a grid medium layer and a grid layer are sequentially formed on the surface of the SOI substrate from bottom to top; a stacking structure is formed by etching the intrinsic silicon layer, the grid medium layer and the grid layer through the photoetching and etching technologies, the stacking structure is partially overlapped with the source electrode and is preset distance away from the drain electrode in the horizontal direction. According to the tunneling field effect transistor and the preparation method of the tunneling field effect transistor, the stacking structure is overlapped with the source electrode so that the tunneling area can be increased, and further a driving current is increased. In addition, the stacking structure is preset distance away from the drain electrode in the horizontal direction, and the bipolar effect in the tunneling field effect transistor can be suppressed through the preset distance, and a subthreshold current is reduced.

Provided are a vertical tunnelling field-effect transistor and a preparation method therefor. The vertical tunnelling field-effect transistor comprises: a source region (1), a first epitaxial layer (2), a gate dielectric layer (3), a gate region (4) and two drain regions (5). A first groove (11) is provided in the source region. A second groove (21) is provided on the first epitaxial layer, and the first epitaxial layer forms a tunnelling channel between the gate region and the source region. Both the gate dielectric layer and the gate region are provided in the second groove. The two drain regions are respectively provided at two opposite sides outside the second groove. Tunnelling can occur in conduction electrons in an area, overlapped with the gate region, of the first groove of the source region, i.e. an overlapping area between the source region and the gate region is enlarged using the first groove, so that a tunnelling area is enlarged. The first epitaxial layer can form the channel between the gate region and the source region, which involves linear tunnelling, and when the electric field direction of the gate region and the electron tunnelling direction of the source region are on the same line, the tunnelling probability is high, thereby improving a tunnelling current.

The invention discloses a Schottky barrier metal oxide semiconductor (MOS) transistor, which comprises a ring-shaped gate electrode (3), a ring-shaped gate dielectric layer (2), a ring-shaped gate electrode side wall (4), a semiconductor substrate, a source region (5) and a ring-shaped drain region (6). The Schottky barrier MOS transistor is characterized in that: the semiconductor substrate is provided with a convex step structure; the source region is positioned on a high plane of a convex step; the ring-shaped drain region surrounds the convex step and is positioned on a low plane; the gate dielectric layer and the gate electrode are positioned at a corner of the convex step, surrounds the step and is raised into a ring shape; and the gate electrode side wall is ring-shaped, surrounds on the outer side of the gate electrode and has a certain thickness to serve as a shelter to form an underlap structure of a drain terminal. The Schottky barrier MOS transistor adopts a step structurecombining a ring-shaped gate structure and an asymmetric source / drain structure, so on the basis of inheriting advantages of traditional SB-MOSFET, the on-state conduction current is improved, a dipolar effect is inhibited, and the process is simplified.

The invention provides a multiple source MOS (metal oxide semiconductor) transistor with impurity segregation and a production method thereof. The multiple source MOS transistor comprises a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region; one end of a control gate extends towards the highly-doped sourceregion to form a T shape; the extended gate region is used as an extension gate; an original control gate region is a main gate; the highly-doped source region is formed by highly doping a semiconductor and is positioned on two sides of the extension gate along the width direction of the source region; and one side of the highly-doped region, which is away from the channel direction, is connectedwith a Schottky source region with impurity segregation. Compared with the present MOSFET (metal-oxide-semiconductor field-effect transistor), under the same process condition and the same size of the active region, higher conducting current, lower leakage current and steeper sub-threshold slope can be obtained.

A tunneling field effect transistor and its forming method, the tunneling field effect transistor comprising: a semiconductor substrate; a first semiconductor layer on the semiconductor substrate, the first semiconductor layer has a first doping type ; an annular groove located in the first semiconductor layer; a first doped region located on the first semiconductor layer and surrounded by the annular groove, the first doped region having a first doping type ; a first channel region located on the first doped region; a second doped region located on the first channel region, the second doped region having a second doping type; The second doped region, the first channel region, the side of the first doped region and the second channel region at the bottom of the annular groove; the gate located in the annular groove; the gate located in the second channel The gate dielectric layer between the region and the gate. Both the tunneling path and the tunneling area of ​​the tunneling field effect transistor are increased, so the performance of the tunneling field effect transistor is improved.

The present invention provides a tunnel field effect transistor and a manufacturing method thereof. The tunnel field effect transistor comprises a substrate; a P-type silylene layer and an N-type silylene layer which form a lamination structure; a grid structure located on the lamination structure; electrodes located on the P-type silylene layer and the N-type silylene layer at the two sides of the grid structure and used for forming a source or a drain with the P-type silylene layer and the N-type silylene layer. The present invention also provides a manufacturing method of the tunnel field effect transistor. The manufacturing method of the tunnel field effect transistor comprises the steps of providing the substrate; forming the P-type silylene layer and the N-type silylene layer to thereby enable the P-type silylene layer and the N-type silylene layer to overlap and contact at the intersection position mutually to form the lamination structure; forming the grid structure on the lamination structure; forming the electrodes on the P-type silylene layer and the N-type silylene layer at the two sides of the grid structure, wherein the electrodes are used to form the source or drain with the P-type silylene layer and the N-type silylene layer. The tunnel field effect transistor of the present invention has a larger tunneling area, and enables the performance to be improved to a certain extent.

The invention provides a composite source MOS (Metal Oxide Semiconductor) transistor with schottky barrier and comb-shaped gate structures and a manufacturing method thereof. The composite source MOS transistor comprises a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a high doped source region and a high doped drain region, wherein one side far away from the channel direction of the high doped source region is connected with a schottky source region; one end of a control gate extends towards the high doped source region; the extended gate region is an extension gate shaped like a comb; the original control gate region is a main gate; the active region covered by the extension gate is likewise a channel region with the substrate material; the high dopedsource region is formed by the high doping of semiconductor and is located on the two sides of each comb of the extension gate; and a schottky junction is formed at the channel under the schottky source region and the extension gate. Compared with the traditional MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), the composite source MOS transistor can obtain a higher conduction current,a lower leakage current and a steeper subthreshold slope under a same technological condition and a same active region size.

A field effect transistor is provided. The field effect transistor includes a semiconductor region formed on a substrate, wherein the semiconductor region comprises an undoped channel region, a source region including a first dopant type, and a drain region including a second dopant type, and wherein the channel region is formed of a group III-V compound semiconductor material. The field effect transistor further includes a high-K gate formed on the channel region, wherein the high-K gate is configured to generate electron tunneling between the source region and the drain region when a gate voltage is applied, and wherein a first contact surface between the source region and the channel region and a second contact surface between the drain region and the channel region are inclined.

The invention relates to a tunneling field effect transistor. A lightly-doped or non-doped substrate ridge protruding out of an insulating layer is formed on the insulating layer; a source region and a drain region are formed on the ridges which are spaced at certain distance, so that a spacing region is formed between the source region and the drain region; an insulating dielectric layer is formed on one lateral surface corresponding to the source region and the spacing region; a gate electrode is formed on the outer lateral surface of the insulating dielectric layer; a source electrode in ohmic contact is formed on the lateral surface which is not covered by the insulating dielectric layer and is parallel to the gate electrode in the source region; and a drain electrode in ohmic contact is formed on the drain region. The tunneling field effect transistor has the advantages that the problem that the electron tunneling probability is reduced due to the fact that a pn junction depletes the widening caused by diffusion of doped atoms is solved; in addition, electron tunneling occurs in the whole source region and the electron tunneling area is great, so that heavy on-state current can be obtained; and vertical tunneling of electrons is simply and conveniently realized by gate electrode-source electrode structures which are arranged in parallel.