Z-type heterojunction tunneling field effect transistor with lightly doped drain structure and preparation method thereof
A technology of tunneling field effect and lightly doped drain, which is applied in semiconductor/solid-state device manufacturing, diodes, semiconductor devices, etc., can solve the problems of application limitation, low driving current, serious bipolar effect, etc., and achieve tunneling probability change Small, increase the drive current, and suppress the effect of bipolar effect
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Embodiment 1
[0032] Embodiment 1, fabricate a tunneling field effect transistor with a length of 3 nm covering the source with the gate.
[0033] Step 1, make SOI substrate, such as figure 2 (a).
[0034] 1a) dry oxygen oxidation on the underlying initial silicon wafer to form a buried oxide layer;
[0035] 1b) A top silicon epitaxial layer is grown on the buried oxide layer by an epitaxial growth process to form an SOI substrate.
[0036] Step 2, etching on both sides of the top layer of silicon to form isolation grooves, such as figure 2 (b).
[0037] 2a) First grow SiO on the top silicon surface of SOI substrate 2 Form the first SiO 2 layer, and then grow the first Si on the surface of the layer 3 N 4 layer, forming the first protective layer;
[0038] 2b) using a photolithography machine to form a shallow trench isolation pattern on the first protection layer by a photolithography process;
[0039] 2c) Etching the shallow trench isolation pattern by using a dry etching proce...
Embodiment 2
[0072] Embodiment 2, fabricate a tunneling field effect transistor with a length of 6 nm covering the source with the gate.
[0073] Step 1, making SOI substrate, such as figure 2 (a).
[0074] The specific implementation of this step is the same as Step 1 of Example 1.
[0075] Step 2, etching on both sides of the top layer of silicon to form isolation grooves, such as figure 2 (b).
[0076] The specific implementation of this step is the same as step 2 of embodiment 1.
[0077] Step 3, forming a doping concentration of 10 on the top silicon surface 20 cm -3 source area, such as figure 2 (c).
[0078] The specific implementation of this step is the same as step 3 of embodiment 1.
[0079] Step 4, forming an intrinsic silicon channel region on the top silicon surface, such as figure 2 (d).
[0080] The specific implementation of this step is the same as step 4 of embodiment 1.
[0081] Step five, prepare a Z-shaped gate region, and cover the source with the gate...
Embodiment 3
[0098] Embodiment 3, fabricating a tunneling field effect transistor with a length of 9 nm covering the source with the gate.
[0099] The first step is to make the SOI substrate, such as figure 2 (a).
[0100] The specific implementation of this step is the same as Step 1 of Example 1.
[0101] The second step is to etch and form isolation grooves on both sides of the top silicon, such as figure 2 (b).
[0102] The specific implementation of this step is the same as step 2 of embodiment 1.
[0103] The third step is to form a doping concentration of 10 on the top silicon surface 20 cm -3 source area, such as figure 2 (c).
[0104] The specific implementation of this step is the same as step 3 of embodiment 1.
[0105] The fourth step is to form an intrinsic silicon channel region on the top silicon surface, such as figure 2 (d).
[0106] The specific implementation of this step is the same as step 4 of embodiment 1.
[0107] The fifth step is to prepare the Z-s...
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