34results about How to "Improved subthreshold characteristics" patented technology

A III-Nitride device has a back-gate disposed in a trench and under and in close proximity to the 2 DEG layer and in lateral alignment with the main gate of the device. A laterally disposed trench is also disposed in a trench and under and in close proximity to the drift region between the gate and drain electrodes of the device. The back-gate is connected to the main gate and the field plate is connected to the source electrode. The back-gate can consist of a highly conductive silicon substrate.

The invention discloses a tunneling field effect transistor (TFET) and a manufacturing method thereof, which belong to the fields of logic devices and circuits of field effect transistors. A high-doping source region of the TFET consists of a P<+> high-doping region and an N<+> high-doping region, and threshold values of a metal-oxide semiconductor field effect transistor (MOSFET) part and a TFET part of a device can be adjusted through ingenious layout variation, so that the performance of a TFET device is improved, and the manufacturing method is simple. Compared with the conventional TFET, the TFET has the advantages that: higher switch-on current can be obtained and a steep subthreshold gradient can be kept by the device under the condition of the same process and the same active region size, so that the TFET is expected to be used in a low power consumption field and has higher practical value.

The invention provides a non-junction field-effect transistor. The non-junction field-effect transistor includes a source region and a drain region, wherein the source region and the drain region are arranged at two sides of a channel region in a central symmetry manner; the channel region, the source region and the drain region are the same in the doping type and the doping concentration; the channel region is provided with a gate dielectric layer and a gate electrode which is arranged on the gate dielectric layer; the source region and the drain region are respectively provided with a source electrode dielectric layer, a source electrode, a source end side electrode, a drain electrode dielectric layer, a drain electrode and a drain end side electrode; isolating dielectric layers isolate the source electrode from the gate electrode; and the work functions of the source electrode and the drain electrode are the work functions which are determined according to the doping type so as to form a conductive carrier layer on the surface of the source region and the surface of the drain region. The non-junction field-effect transistor can accumulate the corresponding type of carriers on the source region and the drain region to perform current transportation by adjusting the metal work functions of the source electrode and the drain electrode. The structure of the non-junction field-effect transistor can restrain the influence of rough edge of a technological fluctuation line on the device performance, can maintain the current driving capability of a non-junction device, and can optimize the subthreshold feature of the non-junction device so as to improve the stability of device.

The invention provides a surrounding gate nanowire field effect transistor and a preparation method thereof. The preparation method comprises the following steps of S1, forming a first fin body isolated from a substrate on the substrate, wherein the first fin body consists of a first region, a second region and a third region which are connected in sequence in the length direction; S2, forming a nanowire structure in the second region of the first fin body; and S3, forming an interface oxide layer, a ferroelectric layer and a gate which are laminated around the exposed surface of the nanowirestructure in sequence, wherein the preparation method also comprises the following steps of forming a source/drain in the first region and the third region, wherein the source/drain is connected withthe two ends of the nanowire structure. By virtue of the preparation method, the gate control capability of the device is improved, electric leakage of the device is lowered, source/drain parasitic resistance of the device is lowered, and the sub threshold value slope of the device can be greatly lower than 60mV/dec.

Devices comprising, and a method for fabricating, a remote doped high performance transistor having improved subthreshold characteristics are disclosed. In one embodiment a field-effect transistor includes a channel layer configured to convey between from a source portion and a drain portion of the transistor when the transistor is in an active state. Further, the field-effect transistor includes a barrier layer adjacent to the channel layer. The barrier layer comprises a delta doped layer configured to provide carriers to the channel layer of the transistor, while preferably substantially retaining dopants in said delta-doped layer.

The invention provides a tunneling field effect transistor comprising a semiconductor substrate, first gates, second gates, first doped regions, and second doped regions. Fins are formed on the semiconductor substrate. Each first gate and the corresponding second gate are respectively formed on the semiconductor substrate at the two sides of the corresponding fin. A gate dielectric layer is formed among each first gate, a first side of the corresponding fin and the semiconductor substrate, and a gate dielectric layer is formed among each second gate, a second side of the corresponding fin and the semiconductor substrate. The first doped regions and the second doped regions are respectively disposed in the semiconductor substrate at one side of the first gates and at one side of the second gates. A narrow tunneling junction is realized by controlling the width of the fins, the tunneling current is increased, and the conduction current is further improved by increasing the effective tunneling area. In addition, defect-related leakage current can be inhibited, and the sub threshold characteristic of devices can be improved.

The invention relates to an oxide semiconductor device which includes an insulating substrate; a source electrode and a drain electrode are oppositely arranged on the insulating substrate; a nanosheet stack part is included and is arranged on the substrate to form a plurality of conducting channels; the nanosheet stack part comprises a plurality of metal oxide semiconductor nanosheets which are vertically stacked to form the nanosheet stack part, and the two ends of the metal oxide semiconductor nanosheets are embedded into the source electrode and the drain electrode respectively; and a surrounding type grid electrode is included and surrounds the periphery of the plurality of metal oxide semiconductor nanosheets in the nanometer stack part. The design of the novel structure gate-all-around OS-TFT (GAA OS-TFT) can significantly improve the sub-threshold characteristic, the current switch ratio and the short channel effect of the device; the working current of the device can be obviously improved by utilizing the design of combining the multiple layers of nanosheets and the supporting structure; the preparation process of the device is compatible with a mainstream CMOS process and is simple; and through the structure design of the surrounding type grid device, the channel carrier mobility can be remarkably improved, the electrical performance of the device is increased, and the reliability and the stability of the device can also be improved.

A tunneling field effect transistor and a manufacturing method thereof, in which the source region (30) is located on both sides of an oxide structure (20), and the epitaxial layer (40) is located on the source region (30) away from the oxide structure ( 20) On one surface, the gate structure (50) is located on the surface of the epitaxial layer (40) away from the source region (30), so that the electric field direction of the gate of the tunneling field effect transistor is consistent with the electron tunneling direction, and the value of the source region The tunneling efficiency of the carriers in the band to the conduction band of the epitaxial layer is high, which can generate a steep sub-threshold swing, which in turn makes the sub-threshold swing of the tunneling field effect transistor lower than 60mV/dec, and the power consumption smaller. Moreover, in the embodiment of the present invention, the epitaxial layer (40) is entirely located between the gate structure (50) and the source region (30), which increases the tunneling area between the epitaxial layer (40) and the source region (30), The subthreshold characteristic of the tunneling field effect transistor is further improved, and the subthreshold swing value of the tunneling field effect transistor is reduced.

The invention belongs to the technical field of integrated circuit semiconductors, and particularly relates to a high-performance silicon-based elliptical gate tunneling field effect transistor. According to the structure, hafnium oxide is used as a substrate oxidation layer; semi-elliptic column type silicon serving as a channel and source-drain is arranged above the hafnium oxide; and an elliptic ring type hafnium oxide gate oxidation layer and a metal gate which have the same length-diameter ratio as the channel cover the channel. The p-type high-concentration boron doping is carried out onthe source end; the light n doping is carried out on the channel; and the n-type high-concentration phosphorus doping is carried out on the drain end. The field effect transistor takes transverse tunneling as a main tunneling mechanism, and can be regarded as a grid-controlled p-i-n junction. The simulation of simulation software shows that the tunneling field effect transistor has a good sub-threshold characteristic; the minimum sub-threshold swing can be as low as 20mV/dec and is smaller than the minimum sub-threshold swing, which is 60mV/dec, of a traditional MOSFET by three times; and a good design foundation is provided for practical development and application of tunneling devices.

The invention relates to a high-integration-level H-shaped source, drain and gate auxiliary control U-shaped channel high-mobility-ratio junction-free transistor. Two independently-controlled gate electrodes including the H-shaped auxiliary control gate electrode and the gate electrode are adopted, the doping concentration of a device is guaranteed to improve the mobility ratio, the device mobility ratio reduction and the device stability reduction caused by strengthening of the random scattering effect under the high doping concentration is avoided, and meanwhile the resistance of source and drain areas is effectively reduced through the H-shaped auxiliary control gate electrode, so that the contradictions that the source and drain resistance will be increased if the doping concentration of a channel of a common junction-free transistor is excessively low, and the device mobility ratio reduction and the device stability reduction will be caused if the doping concentration is excessively high are overcome; meanwhile, U-shaped monocrystalline silicon serves a channel part of the device; compared with a common plane structure, on the premise that the chip area is not increased additionally, the effective channel length is obviously increased to reduce the short channel effect of the device under the deep nanoscale, and therefore the high-integration-level H-shaped source, drain and gate auxiliary control U-shaped channel high-mobility-ratio junction-free transistor is suitable for application and popularization.

This invention provides a doping method for MOS transistor region, which forms a slot at either side of a grid to inject and dope to the transistor region via the slot so as to realize that heavy doped regions at both sides of a channel region are shown as strips, which can shield the influence of the drain field to the channel and source effectively so the device has a good short channel property, since the strip heavy doped regions are at both sides of the channel, the concentration of impurity in the channel region is very low.