36results about How to "Improved subthreshold characteristics" patented technology

The invention discloses a junction-modulated type tunneling field effect transistor and a manufacturing method of the junction-modulated type tunneling field effect transistor, and belongs to the field of field effect transistor logic devices and circuits in CMOS ultra large scale integration (ULSI) circuits. According to the junction-modulated type tunneling field effect transistor, a PN junction provided by a highly-doped source region enclosed on three sides in a vertical channel region is utilized so that the channel region can be effectively used up, a surface channel energy band below a grid can be increased, a device can obtain a steeper energy band and a smaller tunneling barrier width compared with a traditional TFET when subjected to band-band tunneling, the effect of a steep tunnel junction doping density gradient is achieved equivalently, as a result, the subthreshold property of the traditional TFET is improved substantially, and breakover currents of the device are increased at the same time. According to the junction-modulated type tunneling field effect transistor and the manufacturing method of the junction-modulated type tunneling field effect transistor, under the condition that the junction-modulated type tunneling field effect transistor is compatible with an existing CMOS process, the bipolar breakover effect of the device is restrained effectively, parasitic tunneling currents at corners of a source junction with a small size also can be restrained, and the effect of steep source junction doping density can be achieved equivalently.

The invention discloses a method and corresponding device for restraining a tunneling transistor from leaking a current and a method for manufacturing the corresponding device and belongs to the field of field effect transistors and currents in a ULSI of a CMOS. According to the method for restraining the tunneling transistor from leaking the current, an insulating layer is inserted between a source zone and a body zone below a tunnel junction, an insulating layer is not inserted in the portion, between the source zone and a tunnel, of the tunnel junction, so that the source zone and a drain zone in a small-size TFET device are effectively prevented from being directly tunneled and leaking the current, and meanwhile the slope of a subthreshold value can be effectively improved. The method for manufacturing the corresponding device is compatible with the existing CMOS technology.

The invention discloses a tunneling field-effect transistor with a composite-mechanism strip-type grid and a preparation method of the tunneling field-effect transistor and belongs to the field of logic devices and circuits of field-effect transistors in CMOS (Complementary Metal Oxide Semiconductor) ultra-large-scale integrated (ULSI) circuits. The tunneling field-effect transistor has the advantages that the energy band of surface channels under the grid can be improved by changing the shape of the grid and utilizing a depletion effect of PN nodes on the two sides of the strip-type grid, and the subthreshold characteristic of the device is improved; since a composite mechanism is introduced into double-doped source areas, an ON state current of the device is improved; due to an I-shaped design of an active area, body leakage currents, including a source-drain direct tunneling current and a punching current, between the two doped source areas to a doped drain area can be greatly inhibited, and a short-channel effect is inhibited, so that the device with small size can be applied.

The invention provides a non-junction field-effect transistor. The non-junction field-effect transistor includes a source region and a drain region, wherein the source region and the drain region are arranged at two sides of a channel region in a central symmetry manner; the channel region, the source region and the drain region are the same in the doping type and the doping concentration; the channel region is provided with a gate dielectric layer and a gate electrode which is arranged on the gate dielectric layer; the source region and the drain region are respectively provided with a source electrode dielectric layer, a source electrode, a source end side electrode, a drain electrode dielectric layer, a drain electrode and a drain end side electrode; isolating dielectric layers isolate the source electrode from the gate electrode; and the work functions of the source electrode and the drain electrode are the work functions which are determined according to the doping type so as to form a conductive carrier layer on the surface of the source region and the surface of the drain region. The non-junction field-effect transistor can accumulate the corresponding type of carriers on the source region and the drain region to perform current transportation by adjusting the metal work functions of the source electrode and the drain electrode. The structure of the non-junction field-effect transistor can restrain the influence of rough edge of a technological fluctuation line on the device performance, can maintain the current driving capability of a non-junction device, and can optimize the subthreshold feature of the non-junction device so as to improve the stability of device.

The invention provides a tunneling field effect transistor. The tunneling field effect transistor comprises a semiconductor layer, a first gate medium layer and a second gate medium layer which are respectively arranged two opposite surfaces of the semiconductor layer, a source electrode region and a drain electrode region which have different doping types, are respectively arranged at two sides of the semiconductor layer and contact with the semiconductor layer, and a first grid electrode and a second grid electrode which are respectively arranged on the first gate medium layer and the second gate medium layer. According to the tunneling field effect transistor, tunneling junctions are controlled through thickness of a channel region, a larger effective tunneling area is realized, the conduction current is further enhanced, moreover, tunneling is generated in the semiconductor layer, namely, the channel; tunneling layers are non-doped or low-doped tunneling layers, so a leakage current caused by defects can be reduced, and thereby sub-threshold characteristics of devices can be improved; dual-gate control is employed, so bipolar conduction characteristics can be better controlled, and on and off control on the devices can be realized.

Provided are a semiconductor configuration and a method for manufacturing the same. The semiconductor configuration may comprise: a substrate (301); and a fin. The fin comprises a first portion (302-1) and a second portion (302-2) formed sequentially on the substrate, and the first portion and the second portion are T shaped as a whole. The second portion has a reduced thickness at a region corresponding to the first portion.

The present invention provides a method for manufacturing a semiconductor device, the method comprising: step a: providing a semiconductor substrate; step b: forming an insulating layer having an opening and a silicon layer located in the opening on the semiconductor substrate; Forming a heavily doped region in the opening region and the surface layer of the semiconductor substrate below the opening region; step c: forming a channel region, a gate oxide layer and a gate on the insulating layer; step d: forming a gate on the gate A source region and a drain region are formed on both sides; wherein, the source region and the drain region form a Schottky contact with the channel region. Through the manufacturing method of the semiconductor device of the invention, the self-heating effect, leakage-induced potential barrier lowering effect and subthreshold characteristics of the device can be improved.

The invention discloses a heterojunction tunneling field effect transistor with a heterogeneous gate dielectric and a manufacturing method thereof, and mainly solves the problems of small on-state current and serious bipolar effect of the existing tunneling field effect transistor. It includes source, gate, drain, source region, channel region and drain region. Carriers enter the channel region through the source and leave the channel region through the drain. The channel region includes "a" part and " 1", the "1" part includes a first connection end connected to the "one" part, and a second connection end opposite to the first connection end, the second connection end is connected to the drain through the drain region, and the "1" part Two gates are arranged on both sides of the two gates, and two first heterogeneous dielectrics are respectively arranged between the two gates and the "1" part, the gates and the first heterogeneous medium are arranged perpendicular to the second heterogeneous medium, and The sum of the heights of the first heterogeneous medium and the second heterogeneous medium is equal to the "1" part, the height of the gate is equal to that of the first heterogeneous medium, and two sources are respectively arranged on both sides of the "1" part.

The invention provides a tunneling field effect transistor comprising a semiconductor substrate, first gates, second gates, first doped regions, and second doped regions. Fins are formed on the semiconductor substrate. Each first gate and the corresponding second gate are respectively formed on the semiconductor substrate at the two sides of the corresponding fin. A gate dielectric layer is formed among each first gate, a first side of the corresponding fin and the semiconductor substrate, and a gate dielectric layer is formed among each second gate, a second side of the corresponding fin and the semiconductor substrate. The first doped regions and the second doped regions are respectively disposed in the semiconductor substrate at one side of the first gates and at one side of the second gates. A narrow tunneling junction is realized by controlling the width of the fins, the tunneling current is increased, and the conduction current is further improved by increasing the effective tunneling area. In addition, defect-related leakage current can be inhibited, and the sub threshold characteristic of devices can be improved.

The invention provides a method for doping a body region of a MOS transistor, belonging to the technical field of semiconductor integrated circuits and its manufacture. In the method, slits are formed on both sides of the gate electrode, and the ion implantation doping of the body region is performed through the slits. In the present invention, since the heavy doping of the body region is carried out through the slits on both sides of the gate electrode, the heavily doped region is strip-shaped on both sides of the channel region, and the strip-shaped heavily doped region can effectively shield the leakage electric field from affecting The influence of the channel and the source makes the device have good short channel characteristics. Moreover, the strip-shaped heavily doped region is on both sides of the channel, and the impurity concentration in the channel region can be very low, so that the device has high carrier mobility and good subthreshold characteristics. The invention can effectively avoid or alleviate the problems caused by the current conventional body region doping method.

The invention relates to a non-junction folded I-shaped gate field effect transistor with low leakage current, which comprises a silicon substrate of an SOI wafer. An insulation layer of the SOI wafer is arranged above the silicon substrate of the SOI wafer; monocrystalline silicon is arranged above the insulation layer of the SOI wafer; a gate dielectric insulation layer is attached to the surface of the monocrystalline silicon; a folded I-shaped gate electrode is attached to the surface of the gate dielectric insulation layer; the gate electrode is closely attached to the gate dielectric insulation layer; two ends of the upper surface of the monocrystalline silicon are respectively a source electrode and a drain electrode; adjacent monocrystalline silicon and the source electrode and the drain electrode are separated by insulation dielectric layers; and metal is injected to through holes formed after the insulation dielectric layers attached to the upper surface of the monocrystalline silicon and close to the two ends are etched to generate the source electrode and the drain electrode respectively. A low reverse leakage current characteristic can be provided in a condition of ensuring the positive characteristic not to be influenced almost, the power consumption of the device is reduced, and promotion and applications are facilitated.