Junctionless Folded I-Gate Field Effect Transistor with Low Leakage Current

Abstract

The invention relates to a non-junction folded I-shaped gate field effect transistor with low leakage current, which comprises a silicon substrate of an SOI wafer. An insulation layer of the SOI wafer is arranged above the silicon substrate of the SOI wafer; monocrystalline silicon is arranged above the insulation layer of the SOI wafer; a gate dielectric insulation layer is attached to the surface of the monocrystalline silicon; a folded I-shaped gate electrode is attached to the surface of the gate dielectric insulation layer; the gate electrode is closely attached to the gate dielectric insulation layer; two ends of the upper surface of the monocrystalline silicon are respectively a source electrode and a drain electrode; adjacent monocrystalline silicon and the source electrode and the drain electrode are separated by insulation dielectric layers; and metal is injected to through holes formed after the insulation dielectric layers attached to the upper surface of the monocrystalline silicon and close to the two ends are etched to generate the source electrode and the drain electrode respectively. A low reverse leakage current characteristic can be provided in a condition of ensuring the positive characteristic not to be influenced almost, the power consumption of the device is reduced, and promotion and applications are facilitated.

Description

technical field [0001] The invention belongs to the field of ultra-large-scale integrated circuit manufacturing, in particular to a junction-free folded I-shaped gate field-effect transistor structure with low leakage current suitable for low-power integrated circuit manufacturing. Background technique [0002] According to the requirements of Moore's law, the basic unit MOSFET of integrated circuits will become smaller and smaller in size, which will not only make the manufacturing process more difficult, but also cause various adverse effects to become more prominent. On the one hand, the size is proportionally reduced, the channel is getting shorter and shorter, and the gate control ability is weakened, making it difficult for the device to work normally and turn off. On the other hand, the formation of steep PN junctions at the nanoscale requires extremely high heat treatment processes. The FinFETs structure based on multi-gate technology and junctionless field effect t...

AI Technical Summary

Problems solved by technology

Therefore, devices based on FinFETs structure will continue to increase the static power consumption of the device as the size is further reduced.

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