55results about How to "Increase the effective channel length" patented technology

The present invention lengthens gate conductors used in memory chips to limit leakage current, while still allowing the overall size of cells to remain the same. The channel length for each gate is increased by decreasing the size of spaces between gates. Decreases in space size occurs by using photolithographic image enhancement techniques. These techniques allow the space between gate conductors to be smaller while the gate size increases. In addition, a groove may be added that additionally lengthens the effective channel length and provides an additional electrical shield to limit leakage current. These techniques lead to the same density memory cells for a given process with less leakage. Finally, if grooved gate structures are used, having a longer gate conductor allows a three sigma process to be used, which increases yields.

Disclosed are embodiments of a field effect transistor that incorporates an elongated semiconductor body with a spiral-shaped center channel region wrapped one or more times around a gate and with ends that extend outward from the center region in opposite directions away from the gate. Source / drain regions are formed in the end regions by either doping the end regions or by biasing a back gate to impart a preselected Fermi potential on the end regions. This disclosed structure allows the transistor size to be scaled without decreasing the effective channel length to the point where deleterious short-channel effects are exhibited. It further allows the transistor size to be scaled while also allowing the effective channel length to be selectively increased (e.g., by increasing the number of times the channel wraps around the gate). Also, disclosed are embodiments of an associated method of forming the transistor.

A method for manufacturing a semiconductor device having a bulb-type recessed channel including: forming a trench that defines an active region including a channel region having a sidewall and a junction region in a semiconductor substrate; forming a device isolation layer that buries the trench, and forming a sidewall pattern that covers the sidewall of the channel region; forming a bulb-type trench by overlapping with the channel region in the semiconductor substrate, and forming a bottom protrusion having a predetermined space parted from the device isolation layer by removing the sidewall pattern; and forming a gate stack that overlaps with the bulb-type trench and the bottom protrusion.

A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source / drain extension regions, the source / drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source / drain regions and the source / drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.

A memory device comprises a semiconductor substrate of a first conductive type, a memory transistor, a select transistor, a floating junction region, a common source region, and a bit line junction region. The memory transistor positions on the semiconductor substrate and comprises a gate insulating film formed on the semiconductor substrate and a memory transistor gate formed on the gate insulating film. The gate insulating film includes a tunnel insulating film. The select transistor positions on the semiconductor substrate and is separated from the memory transistor gate. The select transistor comprises a gate insulating film formed on the semiconductor substrate and a select transistor gate formed on the gate insulating film. A floating junction region is formed of a second conductive type on the semiconductor substrate below the tunnel insulating film. The common source region of a second conductive type is formed on the semiconductor substrate adjacent to the memory transistor gate and separated from the floating junction region. A bit line junction region of a second conductive type is formed on the semiconductor substrate adjacent to the select transistor gate and is separated from the floating junction region, wherein the common source region includes a single junction region with a first doping concentration, and a depth of the common source region is shallower than a depth of the floating junction region and the bit line junction region.

The invention discloses an SONOS flash memory unit and a manufacturing method thereof, wherein an SONOS component and a selected transistor both adopt enhanced PMOS components, therefore, the substrate bias of the components can be realized without a deep N-well process. A P-type buried channel on the surface of an N-well can provide a great deal of cavities for the programming of the SONOS component, thereby greatly improving the programming efficiency and overcoming the defects of large effective quality and difficult programming of the cavities. The P-type SONOS component can obtain a programming and erasing threshold voltage which is more symmetrical than that of an N-type SONOS component; furthermore, the invention ensures that the drain electrode implantation volume is larger than that of a source electrode, increases the effective channel length and creates conditions for shortening the size of the components by fully utilizing the characteristic of small grid spacing between the two components of the flash memory unit and adopting source-drain ion implantation with large angle and light dope; and finally, the invention further reduces the short channel effect by carrying out bag-shaped ion implantation on the two components of the flash memory unit.

A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source / drain extension regions, the source / drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source / drain regions and the source / drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.

The invention provides a pixel structure comprising a thin film transistor having a first gate electrode and a second gate electrode and an active layer having a first strip part and a second strip part. The first gate electrode is inclined in the extending direction of the orthogonal projection on the plane of the active layer and the extending direction of the first strip part. The second gate electrode is inclined in the extending direction of the orthogonal projection on the plane of the active layer and the extending direction of the second strip part. The first gate electrode and the first strip part of the active layer are obliquely overlapped and the second gate electrode and the second strip part of the active layer are obliquely overlapped so that the effective channel length ofthe channel region of the thin film transistor can be enhanced.

The invention relates to a high-integration-level and high-mobility-ratio source, drain and gate auxiliary control type junction-free transistor. Two independently-controlled gate electrodes including the source and drain control gate electrode and the gate electrode are adopted, so that the high mobility ratio of the device in a channel with the low doping concentration can be guaranteed, and the device mobility ratio reduction and the device stability reduction caused by strengthening of the random scattering effect under the high doping concentration are avoided; meanwhile, the low source and drain resistance can be obtained through the independent control effect of the source and drain control gate electrode and the gate electrode, and therefore the contradictions that the source and drain resistance will be increased if the doping concentration of a channel of a common junction-free transistor is excessively low, and the device mobility ratio reduction and the device stability reduction will be caused if the doping concentration is excessively high are overcome; in addition, the groove-shaped channel design is adopted; compared with a common plane structure, on the premise that a chip area is not additionally increased, the effective channel length is obviously increased to reduce the short channel effect of the device under the deep nanoscale, and therefore the high-integration-level and high-mobility-ratio source, drain and gate auxiliary control type junction-free transistor is suitable for application and popularization.

The invention provides a double-vertical-channel transistor, an integrated circuit memory and a preparation method thereof. A first trench extending along a first direction is formed in the vertical fin; first source / drain regions are formed in the fins at the tops of the two sides of the first trench; a second source / drain region is formed in the fin at the bottom of the first trench; a first gate structure is filled in the first trench and extends along the first direction; the embedded wires are filled in the second trench in the side wall, extending along the second direction, of the vertical fins, so that the first source / drain regions on the two sides of the first trench and the second source / drain region at the bottoms of the first trench respectively form double vertical L-shaped channels, the effective channel length is increased, and the short channel effect is overcome; and the second source / drain region and the electric connection embedded wire thereof are positioned at thebottom of the transistor and do not need to be directly led out from the upper surface, so that isolation at the periphery of the transistor is easier to form, the device area is reduced, the processis simplified and the performance is improved.

A non- volatile storage cell is composed of substrate, grid, the first source electrode / drain electrode area, composite dielectric layer and the second source electrode / drain electrode area. It is featured as setting a slot on substrate; placing grid in slot, the first source electrode / drain electrode area at slot bottom; setting composite dielectric layer between grid and slot surface and placing the second source electrode / drain electrode area in substrate at two side of grid.

Provided is a complementary metal oxide semiconductor (CMOS) inverter layout for increasing an effective channel length. The CMOS inverter layout may include first and second conductive MOS transistors respectively formed in first and second active regions, metal lines electrically connecting the first and second conductive MOS transistors, and one or more gate electrodes electrically connecting the gates of the first and second conductive MOS transistors. The widths of one or more gate electrodes may be set to a reduced and / or minimum feature size to reduce and / or minimize a process variation and a layout area of the CMOS inverter. Also, the first and second conductive MOS transistors may be connected in series via the metal lines to increase an effective channel length, thereby realizing a layout of the CMOS inverter having a longer delay than a conventional CMOS inverter.

The invention discloses a channel structure of an MOS transistor, which is used in the power MOS transistor. The surface of a silicon substrate in a channel zone is provided with a plurality of slots of which the lengthwise direction is the same as the moving direction of the current in the channel zone when the MOS transistor works. Because the channel zone is additionally provided with the slots, the channel is changed from a single plane to multi-planes, so that under conditions of not changing the size of the device, the effective length of the channel of the device is increased, and the driving capacity of the device is also enhanced.

The invention relates to a high-integration-level source, drain and gate auxiliary control U-shaped channel high-mobility-ratio junction-free transistor shaped like the Chinese character 'ri'. Two independently-controlled gate electrodes including the auxiliary control gate electrode shaped like the Chinese character 'ri' and the gate electrode are adopted, it is guaranteed that the dosing concentration of the device is reduced to improve the mobility ratio, and the device mobility ratio reduction and the device stability reduction caused by strengthening of the random scattering effect under the high doping concentration are avoided; meanwhile, the resistance of source and drain areas is effectively reduced through the auxiliary control gate electrode shaped like the Chinese character 'ri', so that the contradictions that the source and drain resistance will be increased if the doping concentration of a channel of a common junction-free transistor is excessively low, and the device mobility ratio reduction and the device stability reduction will be caused if the doping concentration is excessively high are overcome; meanwhile, U-shaped monocrystalline silicon serves a channel part of the device; compared with a common plane structure, on the premise that the chip area is not additionally increased, the effective channel length is obviously increased to reduce the short channel effect of the device under the deep nanoscale, and therefore the high-integration-level source, drain and gate auxiliary control U-shaped channel high-mobility-ratio junction-free transistor shaped like the Chinese character 'ri' is suitable for application and popularization.

The present invention relates to a method of manufacturing a semiconductor memory device and a semiconductor memory device manufactured using the same. A method of manufacturing a semiconductor device comprises defining source / drain regions in semiconductor substrate through an etch process using a mask, and forming a gate and source / drain by depositing a conductive material over the defined regions and the semiconductor substrate and patterning the conductive material.

A sub-word line driver includes a substrate, a plurality of gate lines and at least one gate tab. The substrate includes a plurality of isolation areas and a plurality of active areas, where the two active areas are separated by each isolation area, and the isolation areas and the active areas are extended in a first direction and are arranged in a second direction perpendicular to the first direction. The plurality of gate lines are formed on the substrate, where the gate lines are extended in a second direction and are arranged in the first direction. The at least one gate tab is formed on the substrate, where the at least one gate tab is extended in the first direction to cover the isolation area. Incorrect operation of the sub-word line driver may be prevented, and a power consumption of the sub-word line driver may be reduced.

A nonvolatile memory device includes a control gate formed along a first direction over a substrate, an active region formed over the substrate, the active region being defined along a second direction crossing the control gate and including a fin type protruding portion having rounded top corners at a region where the control gate and the active region overlap, a floating gate formed over a surface of the protruding portion of the active region below the control gate and formed to a substantially uniform thickness along the surface profile of the protruding portion of the active region, a tunneling insulation layer formed between the floating gate and the active region, and a dielectric layer formed between the floating gate and the control gate.

The invention provides a method for reducing dark current of an image sensor. The method comprises preparation of a photodiode and a transistor. The preparation of the transistor comprises following steps of firstly forming grid electrodes of four transistors; forming light dope drain regions of a reset pipe, an amplifying pipe and a selecting pipe; then, forming corresponding side walls on grid electrode side walls of the rest pipe, the amplifying pipe, the selection pipe and a transferring pipe; and at last, forming a light dope drain region of the transferring pipe on the substrate of a semiconductor at the bottom of the outer side of the side wall of the transferring pipe. Thus, effective channel length of the transferring pipe is increased, electric field in the channel direction is reduced and probability of generation of thermal electrons is reduced, thereby reducing dark current of the image sensor.

The present disclosure provides a semiconductor device. The semiconductor device comprises a substrate, a plurality of isolation regions in the substrate and an active region surrounded by the isolation regions. A p-type doped region is interposed between two n-type doped regions in the substrate. A buried gate structure is formed in the substrate and disposed between the p-type doped region and the n-type doped region. The buried gate structure comprises a gate conductive material, a gate insulating layer disposed over the gate conductive material and a gate liner surrounding the gate conductive material and the gate insulating layer. A plurality of contact plugs are formed on the p-type doped region and the plurality of n-type doped regions.

The invention provides a method for increasing the length of an effective channel of a PMOS, which comprises the following steps of: making an n-well and a p-well in a substrate; making a first polysilicon gate on the n-well and making a second polysilicon gate on the p-well; growing a first oxidation layer; injecting lightly doped source / drain in an n-well area; respectively growing a second oxidation layer on the surface of the n-well and the p-well; injecting lightly doped source / drain in a p-well area; respectively growing a silicon nitride layer and a third oxidation layer in the n-well and the p-well areas; etching the first oxidation layer, the second oxidation layer, the silicon nitride layer and the third oxidation layer; respectively forming a side wall around the polysilicon gates of the n-well and the p-well; injecting heavily doped source / drain in the n-well area; and injecting heavily doped source / drain in the p-well area. The method moves the step of injecting the lightly doped source / drain in the p-well area between the step of growing the second oxidation layer and the step of growing the silicon nitride layer and increases the length of the effective channel of the PMOS by using the second oxidation layer.

A memory cell is provided. The memory cell includes a substrate, an isolation layer, a gate, a charge storage structure, a first source / drain region, a second source / drain region and a channel layer. The isolation layer is disposed over the substrate. The gate is disposed over the isolation layer. The charge storage structure is disposed over the isolation layer and the gate. The first source / drain region is disposed over the charge storage structure at two sides of the gate. The second source / drain region is disposed over the charge storage structure at top of the gate. The channel layer is disposed over the charge storage structure at sidewall of the gate and is electrically connected with the first source / drain region and the second source / drain region.

The invention discloses a MOSFET structure which belongs to the technical field of semiconductor devices and comprises a substrate electrode, a substrate, a channel region, a source region, a drain region, a source electrode, a drain electrode, a gate oxide layer and a gate electrode. The channel region with a non-planar surface is formed in a substrate region built in the substrate, and the source region and the drain region are arranged on both sides of the channel region respectively. The source electrode and the drain electrode are correspondingly arranged in the source region and the drain region respectively. The gate oxide layer covers the surface of the non-planar channel region. The gate electrode is arranged on the surface of the gate oxide layer, and both ends of the gate electrode are spaced from the source electrode and the drain electrode. Both ends of the gate electrode respectively extend to the source region and the drain region to form overlap. According to the invention, the non-planar channel MOSFET structure is used to reduce the electric field peak of the drain region and increase the effective channel length of a device; a leakage-induced barrier reducing effect is improve and suppressed; a short channel effect is suppressed; the high electric field of the drain region is reduced; the generation of hot carriers is suppressed; and the stability of the device is improved.

The invention provides a semiconductor device and a preparation method thereof. A second trench extending along a second direction is formed in a semiconductor substrate. U-shaped fins are arranged onthe two sides of the second trench in a staggered mode. The U-shaped fin is provided with a first trench extending along a first direction. The first source / drain regions are formed in the fins at the tops of the two sides of the first trench; a second source / drain region is formed in the fin at the bottom of the first trench; a gate line is filled in the first trench and extends along the firstdirection; the embedded wire is filled in the second trench extending along the second direction, so that the two first source / drain regions in the U-shaped fin respectively form double vertical L-shaped channels with the second source / drain region, the effective channel length is favorably increased, the short channel effect is overcome, and the smaller feature size and the higher integration degree are further favorably realized; and the U-shaped fins on the two sides of the second trench are arranged in a staggered manner, so that the coupling effect between adjacent active regions can be improved, and the device performance can be improved.