55results about How to "Increase the effective channel length" patented technology

The present invention lengthens gate conductors used in memory chips to limit leakage current, while still allowing the overall size of cells to remain the same. The channel length for each gate is increased by decreasing the size of spaces between gates. Decreases in space size occurs by using photolithographic image enhancement techniques. These techniques allow the space between gate conductors to be smaller while the gate size increases. In addition, a groove may be added that additionally lengthens the effective channel length and provides an additional electrical shield to limit leakage current. These techniques lead to the same density memory cells for a given process with less leakage. Finally, if grooved gate structures are used, having a longer gate conductor allows a three sigma process to be used, which increases yields.

The invention relates to a high-integration-level and high-mobility-ratio source, drain and gate auxiliary control type junction-free transistor. Two independently-controlled gate electrodes including the source and drain control gate electrode and the gate electrode are adopted, so that the high mobility ratio of the device in a channel with the low doping concentration can be guaranteed, and the device mobility ratio reduction and the device stability reduction caused by strengthening of the random scattering effect under the high doping concentration are avoided; meanwhile, the low source and drain resistance can be obtained through the independent control effect of the source and drain control gate electrode and the gate electrode, and therefore the contradictions that the source and drain resistance will be increased if the doping concentration of a channel of a common junction-free transistor is excessively low, and the device mobility ratio reduction and the device stability reduction will be caused if the doping concentration is excessively high are overcome; in addition, the groove-shaped channel design is adopted; compared with a common plane structure, on the premise that a chip area is not additionally increased, the effective channel length is obviously increased to reduce the short channel effect of the device under the deep nanoscale, and therefore the high-integration-level and high-mobility-ratio source, drain and gate auxiliary control type junction-free transistor is suitable for application and popularization.

The invention provides a double-vertical-channel transistor, an integrated circuit memory and a preparation method thereof. A first trench extending along a first direction is formed in the vertical fin; first source/drain regions are formed in the fins at the tops of the two sides of the first trench; a second source/drain region is formed in the fin at the bottom of the first trench; a first gate structure is filled in the first trench and extends along the first direction; the embedded wires are filled in the second trench in the side wall, extending along the second direction, of the vertical fins, so that the first source/drain regions on the two sides of the first trench and the second source/drain region at the bottoms of the first trench respectively form double vertical L-shaped channels, the effective channel length is increased, and the short channel effect is overcome; and the second source/drain region and the electric connection embedded wire thereof are positioned at thebottom of the transistor and do not need to be directly led out from the upper surface, so that isolation at the periphery of the transistor is easier to form, the device area is reduced, the processis simplified and the performance is improved.

A non- volatile storage cell is composed of substrate, grid, the first source electrode / drain electrode area, composite dielectric layer and the second source electrode / drain electrode area. It is featured as setting a slot on substrate; placing grid in slot, the first source electrode / drain electrode area at slot bottom; setting composite dielectric layer between grid and slot surface and placing the second source electrode / drain electrode area in substrate at two side of grid.

Provided is a complementary metal oxide semiconductor (CMOS) inverter layout for increasing an effective channel length. The CMOS inverter layout may include first and second conductive MOS transistors respectively formed in first and second active regions, metal lines electrically connecting the first and second conductive MOS transistors, and one or more gate electrodes electrically connecting the gates of the first and second conductive MOS transistors. The widths of one or more gate electrodes may be set to a reduced and/or minimum feature size to reduce and/or minimize a process variation and a layout area of the CMOS inverter. Also, the first and second conductive MOS transistors may be connected in series via the metal lines to increase an effective channel length, thereby realizing a layout of the CMOS inverter having a longer delay than a conventional CMOS inverter.

The invention discloses a channel structure of an MOS transistor, which is used in the power MOS transistor. The surface of a silicon substrate in a channel zone is provided with a plurality of slots of which the lengthwise direction is the same as the moving direction of the current in the channel zone when the MOS transistor works. Because the channel zone is additionally provided with the slots, the channel is changed from a single plane to multi-planes, so that under conditions of not changing the size of the device, the effective length of the channel of the device is increased, and the driving capacity of the device is also enhanced.

The present invention relates to a method of manufacturing a semiconductor memory device and a semiconductor memory device manufactured using the same. A method of manufacturing a semiconductor device comprises defining source/drain regions in semiconductor substrate through an etch process using a mask, and forming a gate and source/drain by depositing a conductive material over the defined regions and the semiconductor substrate and patterning the conductive material.

The invention provides a method for reducing dark current of an image sensor. The method comprises preparation of a photodiode and a transistor. The preparation of the transistor comprises following steps of firstly forming grid electrodes of four transistors; forming light dope drain regions of a reset pipe, an amplifying pipe and a selecting pipe; then, forming corresponding side walls on grid electrode side walls of the rest pipe, the amplifying pipe, the selection pipe and a transferring pipe; and at last, forming a light dope drain region of the transferring pipe on the substrate of a semiconductor at the bottom of the outer side of the side wall of the transferring pipe. Thus, effective channel length of the transferring pipe is increased, electric field in the channel direction is reduced and probability of generation of thermal electrons is reduced, thereby reducing dark current of the image sensor.

A memory cell is provided. The memory cell includes a substrate, an isolation layer, a gate, a charge storage structure, a first source/drain region, a second source/drain region and a channel layer. The isolation layer is disposed over the substrate. The gate is disposed over the isolation layer. The charge storage structure is disposed over the isolation layer and the gate. The first source/drain region is disposed over the charge storage structure at two sides of the gate. The second source/drain region is disposed over the charge storage structure at top of the gate. The channel layer is disposed over the charge storage structure at sidewall of the gate and is electrically connected with the first source/drain region and the second source/drain region.