Double-vertical-channel transistor, integrated circuit memory and preparation method thereof

Abstract

The invention provides a double-vertical-channel transistor, an integrated circuit memory and a preparation method thereof. A first trench extending along a first direction is formed in the vertical fin; first source / drain regions are formed in the fins at the tops of the two sides of the first trench; a second source / drain region is formed in the fin at the bottom of the first trench; a first gate structure is filled in the first trench and extends along the first direction; the embedded wires are filled in the second trench in the side wall, extending along the second direction, of the vertical fins, so that the first source / drain regions on the two sides of the first trench and the second source / drain region at the bottoms of the first trench respectively form double vertical L-shaped channels, the effective channel length is increased, and the short channel effect is overcome; and the second source / drain region and the electric connection embedded wire thereof are positioned at thebottom of the transistor and do not need to be directly led out from the upper surface, so that isolation at the periphery of the transistor is easier to form, the device area is reduced, the processis simplified and the performance is improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a double vertical channel transistor, an integrated circuit memory and a preparation method thereof. Background technique [0002] Vertical surrounding gate transistor (SGT) with buried bit line, which uses increased isolation rules to reduce the difficulty of shallow trench isolation manufacturing, and its process includes a lengthy buried bit line process Steps, the process steps of spin coating dielectric layer (SOD), the process steps of metal and N-type doped polysilicon to define the gate length of the transistor, the process is complicated, and the stability of the threshold voltage of the memory array is also significantly reduced. And under the limitation of the vertical size, it is impossible to reduce the change of the threshold voltage (Vth) with a longer channel length. [0003] Therefore, there is a need for a new double vertical channel tr...

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Problems solved by technology

[0002] Vertical surrounding gate transistor (SGT) with buried bit line, which uses increased isolation rules to reduce the difficulty of shallow trench isolation manufacturing, and its process includes a lengthy buried bit line process Steps, the process steps of spin coating dielectric layer (SOD), the process steps of metal and N-type doped polysilicon to define the gate length of the transistor, the process is complicated, and the stability of the threshold voltage of the memory array is also significantly reduced. And under the limitation of the vertical size, it is impossible to reduce the change of the threshold voltage (Vth) with a longer channel length.

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