33 results about "Planar channel" patented technology

A cable clamp includes a housing having two substantially parallel and co-planar channels therethrough. At least one restraining member is disposed within the housing between the two channels, also substantially parallel and co-planar therewith. A surgical cable is passed through the first channel, around a bone or other structure, and through the second channel. The restraining member may then be actuated to impinge against the surgical wire or cable, simultaneously constraining the surgical wire or cable within both channels between the restraining member (an inner wall) and the housing (an outer wall). For example, the restraining member may be an expansion member that, when expanded as by driving a wedge between two restraining arms, reduces the size of the channels such that the surgical wire or cable can no longer pass freely therethrough.

The invention belongs to the technical field of manufacturing of semiconductor devices and particularly relates to a method for manufacturing a semi-floating gate device with planar channels. The method for manufacturing the semi-floating gate device with the planar channels comprises the steps that the semi-floating gate device with the planar channels is manufactured through a post-gate technology; after a source contact area and a drain contact area are formed, a polycrystalline silicone control gate sacrificial material is removed through etching firstly, secondly a metal control gate material occupies the position originally occupied by the polycrystalline silicone control gate sacrificial material, and then a metal control gate is formed. The metal control gate can be prevented from being damaged in a high-temperature annealing process of a source contact area and a drain contact area, and the performance of the semi-floating gate device with the planar channels is improved. In addition, according to the method, self-alignment technology is adopted to manufacture the source contact area and the drain contact area of the semi-floating gate device, the technology process is simple and stable, and production cost is reduced.

A multiplexed, absorbance-based microfabricated chip electrophoresis system, microfabricated chip, and method of use are included for the detection and identification of protein species. The microfabricated chip electrophoresis system capable of analyzing multiple samples simultaneously. The system uses a microfabricated chip having a sample chamber for first dimension separation of a sample, a first planar array of channels for second dimension separation of the sample approximately perpendicular the sample chamber, and a barrier separating the sample chamber from the first planar array of channels during the first dimension separation. In use, the sample is placed into a sample chamber, a barrier is established around the sample chamber, the sample is isoelectric focused within the sample chamber, the barrier is then removed, and the sample separated in the first array of channels by molecular weight.

A three-dimensional (3-D) nonvolatile memory device includes vertical channel layers protruded from a substrate, interlayer insulating layers and memory cells, which are alternately stacked along the vertical channel layers, and select transistors including planar channel layers, each contacted with at least one of the vertical channel layers and being parallel to the substrate, and gate insulating layers formed over the planar channel layers.

Disclosed is a complementary CMOS device having a first FET with sidewall channels and a second FET with a planar channel. The first FET can be a p-FET and the second FET can be an n-FET or vice versa. The conductor used to form the gate electrodes of the different type FETs is different and is pre-selected to optimize performance. For example, a p-FET gate electrode material can have a work function near the valence band and an n-FET gate electrode material can have a work function near the conduction band. The first gate electrodes of the first FET are located adjacent to the sidewall channels and the second gate electrode of the second FET is located above the planar channel. However, the device structure is unique in that the second gate electrode extends laterally above the first FET and is electrically coupled to the first gate electrodes.

The invention discloses a vertical power metal-oxide-semiconductor field-effect transistor cell with a planar channel, which comprises an N+ silicon substrate with a drain electrode. The N-type drift layer with low doping concentration is longer than the substrate. Alternate N-type columns and P-type columns are formed on the drift layer and have higher doping concentration. An N-type layer having a higher doping concentration than the drift region is then formed and etched with sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed on the lateral channel of the P-well near the sidewall to act as a vertical field plate. A source electrode contacts the P-well and the source region. A positive gate voltage inverts the lateral channel and increases conductivity along the sidewalls. The current between the source and the drain flows laterally and then vertically through various N layers. Turn-on resistance is reduced and the breakdown voltage is increased.

The invention discloses a mixed-crystal-face strain-Si vertical-channel CMOS (complementary metal oxide semiconductor) integrated device and a preparation method. The preparation method includes: preparing an SOI (silicon on insulator) substrate, wherein an upper substrate is a crystal face (100) and a lower substrate is a crystal face (110); etching a deep trench in a PMOS (P-channel metal oxide semiconductor) active region at the temperature of 600-800 DEG C, selectively growing a strain Si PMOS active layer on a multi-layer structure of the crystal face (110), and preparing a compression strain PMOS of a vertical channel on the active layer; and etching a deep trench on an NMOS (N-channel metal oxide semiconductor) active region, selectively growing a strain Si NMOS active layer on a multi-layer structure of the crystal face (100), preparing a tensile strain NMOS of a planar channel on an epitaxial layer, and forming a mixed-crystal-face strain-Si CMOS integrated circuit with a conducting channel of 22-45nm. By the mixed-crystal-face strain-Si vertical-channel CMOS integrated device and the preparation method, the characteristics that migration rate of strain Si materials is higher than that of Si materials and the strain and the migration rate of the strain Si materials are anisotropic are fully used, and the mixed-crystal-face strain-Si CMOS integrated device and the mixed-crystal-face strain-Si CMOS integrated circuit which are excellent in performance are prepared on the basis of the SOI substrate.

A method is provided for operation a field effect transistor arrangement, the field effect transistor arrangement having a planar channel layer including a semiconductor material, a whole surface of an underside of the planar channel layer being applied to a top side of an electrically insulating substrate layer and an upper side of the planar channel layer being covered by an electrically insulating electrode insulation layer, the arrangement having a source electrode disposed by a first side edge of the planar channel layer and having a drain electrode disposed by a second side edge of the planar channel layer, and having a control electrode arranged above the planar channel layer between the source electrode and the drain electrode, wherein an adjusting electrode is arranged on an underside of the substrate layer, and a first contact region between the source electrode and the planar channel layer and a second contact region between the drain electrode and the planar channel layer are each a Schottky barrier, wherein a respective barrier control electrode is arranged between the first contact region of the source electrode and the control electrode and between the second contact region of the drain electrode and the control electrode, the method including providing a first electric potential to the control electrode, providing a second electric potential to the barrier electrodes, and providing a third electric potential to the adjusting electrode.

The invention discloses a semiconductor memory device, which comprises a source, a drain, a floating gate region, a control gate, a planar channel region and a gate controlled diode, wherein the gate controlled diode is used for connecting the floating gate region and the drain; and in the semiconductor memory device, the floating gate region is used for memorizing information, the gate controlled diode is used for connecting a floating gate and a substrate, and the floating gate is charged or discharged by the gate controlled diode. The semiconductor memory device is manufactured by using a self-alignment process, and the process is simple and stable; and in the invention, manufacturing of a logic circuit and a flash memory device is compatible by using a planar channel structure.