33 results about "Planar channel" patented technology

A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g, 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).

A three-dimensional (3-D) nonvolatile memory device includes vertical channel layers protruded from a substrate, interlayer insulating layers and memory cells, which are alternately stacked along the vertical channel layers, and select transistors including planar channel layers, each contacted with at least one of the vertical channel layers and being parallel to the substrate, and gate insulating layers formed over the planar channel layers.

The invention discloses a semiconductor memory device, which comprises at least one semiconductor substrate, a source electrode, a drain electrode, a floating gate area, two control gate electrodes and a gate control p-n junction diode. The gate control p-n junction diode is used for connecting the floating gate area and the substrate. In the semiconductor memory device, the floating gate area is used for storing information, and charging and discharging the floating gate area through the gate control p-n junction diode is realized. Furthermore, the invention also discloses a manufacturing method of the semiconductor memory device, a self-aligning process is adopted for manufacturing, and the process is simple and stable. Moreover, a planar channel structure is adopted, and the method is compatible with manufacturing of logic devices and flash memory devices.

A cable clamp includes a housing having two substantially parallel and co-planar channels therethrough. At least one restraining member is disposed within the housing between the two channels, also substantially parallel and co-planar therewith. A surgical cable is passed through the first channel, around a bone or other structure, and through the second channel. The restraining member may then be actuated to impinge against the surgical wire or cable, simultaneously constraining the surgical wire or cable within both channels between the restraining member (an inner wall) and the housing (an outer wall). For example, the restraining member may be an expansion member that, when expanded as by driving a wedge between two restraining arms, reduces the size of the channels such that the surgical wire or cable can no longer pass freely therethrough.

A semiconductor integrated circuit device and a method of fabricating the same are provided. An embodiment of the semiconductor integrated circuit device includes a substrate having a cell region and a peripheral circuit region. A recess channel transistor may be formed in the cell region and include a source/drain region, a recess channel formed between the source/drain region, a gate insulation layer formed in the recess channel, and a gate formed on the gate insulation layer in a self-aligned manner. A planar channel transistor may further be formed in the peripheral circuit region and include a source/drain region, a planar channel formed between the source/drain region, a gate insulation layer formed in the planar channel, and a gate formed on the gate insulation layer in a self-aligned manner.

A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. Alternating N and P-type columns are formed over the drift layer with a higher dopant concentration. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and next to the sidewalls as a vertical field plate. A source electrode contacts the P-well and source region. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls. Current between the source and drain flows laterally and then vertically through the various N layers. On resistance is reduced and the breakdown voltage is increased.

The invention belongs to the technology field of irrigation. The outflow constant structure comprises: an upper plane channel, wherein a plurality of primary energy dissipating units are arranged in sequence inside the upper plane channel and a water inlet is arranged at the front end of the upper planar channel; a lower plane channel, wherein a plurality of secondary energy dissipating units arearranged in sequence inside the lower plane channel, a plurality of primary energy dissipating units are respectively arranged corresponding to the plurality of the secondary energy dissipating units,and corresponding communication holes are arranged between the corresponding primary energy dissipating units and the secondary energy dissipating units; and an outlet channel, wherein each of the secondary energy dissipating units is connected to the outlet channel through an outlet and a constant flow port is arranged on the outlet channel. The invention further discloses an outflow constant method. The overall structure of the outflow constant structure has no moving parts, the energy dissipating path is automatically selected according to the water inlet pressure through the four-dimensional energy dissipation, thereby realizing constant flow and constant pressure on the outlet.

A planar MESFET transistor includes a plurality of FET elements. Each FET element includes a doped planar channel, and source and drain coupled to the ends of the channel. A gate conductor extends over a portion of the channel at a location lying between the source and drain, a first predetermined distance from the drain. A field plate is connected to the gate conductor, and extends toward the drain a second predetermined distance, isolated from the channel except at its gate conductor connection by a dielectric material.

In the manufacture of a planar channel-type MOS transistor, an n-well is formed in a predetermined region of a p-type semiconductor substrate to define a p-channel transistor region in which element forming regions are located as a p-type active region and a p-type gate electrode. A p-type substrate region adjacent to the p-channel transistor region defines an n-channel transistor region in which element forming regions are located as an n-type active region and an n-type gate electrode. Titanium silicide is formed in self-alignment as an upper layer of each of the p- and n-type active regions and p- and n-type gate electrodes. A boundary of the p- and n-type gate electrodes is a nondoped region where the titanium silicide is formed in an increased thickness as compared to that of the titanium silicide formed on the remaining portion of the gate electrodes.

The invention provides a system and method for adjusting the length of a channel of a flat portion in an extrusion die. The extrusion die having an adjustable flat channel can be formed from a mold body including a first mold body portion and a second mold body portion, a first lip body, a second lip body, and a flat channel body. The extrusion die can have a flow channel that includes a flat portion channel terminating in the exit aperture. The flow channel may be defined on one side by a first mold body portion, a flat portion channel body and a first lip body. The flow channel may be defined on the opposite side by the second mold body portion and the second lip body. In some examples, the length of the channel of the flat portion may be adjusted by configuring the planar channel body and/or the first lip body to move across the width of the flow channel.

The invention discloses a conformal array antenna design method, computer equipment and a storage medium. The method comprises the following steps: determining the form of a microstrip patch antenna; based on the micro-strip patch antenna and the preset bending curvature radius of the conformal array antenna, performing simulation and optimization design on the unit antenna by using three-dimensional electromagnetic field simulation software; the unit antennas form an array antenna, simulation optimization is carried out, and the final size of the antenna unit is determined; calculating corresponding plane channel position coordinates after the channel position coordinates on the curved surface of the conformal array antenna are flattened; writing pattern coordinates of the array antenna in the drawing tool software by utilizing tabulation software, writing a corresponding drawing command symbol, and copying and pasting the command symbol in a command line of the drawing tool software to complete pattern drawing of the array antenna; drawing out and carrying out PCB (Printed Circuit Board) processing; and bending, attaching and fixing the array antenna in the form of the plane PCB on the curved-surface carrier plate to form the final conformal array antenna. The method is wide in applicability, efficient and feasible.

The embodiment of the invention provides an integrated circuit and a method for forming a semiconductor structure. The gate-all-around (GAA) nanowire transistor is provided with a plurality of nanowire channels which are vertically stacked, a first grid dielectric layer wrapping the nanowire channels and a first grid electrode wrapping the first grid dielectric layer. The GAA nanowire transistorshas a plurality of vertically stacked nanosheet channels, a second gate dielectric layer wrapping the nanosheet channels, and a second gate electrode wrapping the second gate dielectric layer. The planar device has a planar channel, a third gate dielectric layer on the planar channel, and a third gate electrode on the third gate dielectric layer. The first and second gate dielectric layers have the same thickness. The third gate dielectric layer is thicker than the first and second gate dielectric layers. The widths of the nanowire channels and the nanosheet channels are smaller than the widthof the planar channel.